EVAL-AD5371EBZ Analog Devices Inc, EVAL-AD5371EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5371EBZ
• Description: BOARD EVAL FOR AD5371
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5371EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5371
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
LVDS INTERFACE (REDUCED RANGE LINK)
POWER REQUIREMENTS
1
2
3
AC CHARACTERISTICS
DV
and DAC offset registers at default values; all specifications T
Table 3. AC Characteristics
Parameter
DYNAMIC PERFORMANCE
1
Typical specifications are at 25°C.
Guaranteed by design and characterization; not production tested.
θ
Guaranteed by design and characterization; not production tested.
JA
Digital Inputs
DV
V
V
Power Supply Sensitivity
DI
I
I
Power Dissipation Unloaded (P)
Power-Down Mode
Junction Temperature
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
DD
SS
CC
represents the package thermal impedance.
DD
SS
CC
Input Differential Threshold
External Termination Resistance
Input Voltage Range
Differential Input Voltage
∆Full Scale/∆V
∆Full Scale/∆V
∆Full Scale/∆DV
DI
I
I
CC
DD
SS
= 2.5 V; V
CC
2
DD
= 15 V; V
DD
SS
CC
3
2
SS
1
= −15 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C
Min
875
–0.1
80
100
2.5
9
−16.5
Min
Typ
20
1
5
100
20
0.2
0.02
250
Typ
100
−75
−75
−90
280
5
35
−35
Max
30
10
Rev. B | Page 5 of 28
MIN
1
to T
Max
1575
+0.1
132
5.5
16.5
−4.5
2
18
20
−18
−20
130
Unit
μs
μs
V/μs
nV-s
mV
dB
nV-s
nV-s
nV-s
nV/√Hz
MAX
, unless otherwise noted.
Unit
mV
V
Ω
mV
V
V
V
dB
dB
dB
mA
mA
mA
mA
mA
mW
μA
μA
μA
°C
Test Conditions/Comments
Settling to 1 LSB from a full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
VREF0, VREF1, VREF2 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
V
REF
= 0 V
Test Conditions/Comments
DV
operating conditions
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
V
Control register power-down bit set
T
J
L
SS
= T
= 200 pF; R
CC
= −8 V, V
= 5.5 V, V
A
+ P
TOTAL
DD
IH
= 9.5 V, DV
× θ
L
= 10 kΩ; gain (M), offset (C),
= DV
JA
CC
, V
IL
CC
= GND; normal
= 2.5 V
1
AD5371