EVAL-AD5371EBZ Analog Devices Inc, EVAL-AD5371EBZ Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD5371EBZ
• Description: BOARD EVAL FOR AD5371
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5371EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5371
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL DESCRIPTION
The AD5371
or 100-ball CSP_BGA. The device provides buffered voltage
outputs with a span of 4× the reference voltage. The gain and
offset of each DAC can be independently trimmed to remove
errors. For even greater flexibility, the device is divided into five
groups of eight DACs. Three offset DACs allow the output range
of the groups to be adjusted. Group 0 can be adjusted by Offset
DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2
to Group 4 can be adjusted by Offset DAC 2.
The AD5371 offers guaranteed operation over a wide supply
range, with V
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
1
Table 1. High Channel Count Bipolar DACs
Model
AD5360
AD5361
AD5362
AD5363
AD5370
AD5371
AD5372
AD5373
AD5378
AD5379
Protected by U.S. Patent No. 5,969,657; other patents pending.
1
SS
contains 40 14-bit DACs in a single 80-lead LQFP
from −16.5 V to −4.5 V and V
Resolution (Bits)
16
14
16
14
16
14
16
14
14
14
Nominal Output Span
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
±8.75 V
±8.75 V
REF
REF
REF
REF
REF
REF
REF
REF
(20 V)
(20 V)
(20 V)
(20 V)
(12 V)
(12 V)
(12 V)
(12 V)
DD
from 9 V to
Rev. B | Page 3 of 28
The AD5371 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz. It also has a
100 MHz low voltage differential signaling (LVDS) serial
interface.
The DAC registers are updated on reception of new data. All the
outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Output Channels
16
16
8
8
40
40
32
32
32
40
Linearity Error (LSB)
±4
±1
±4
±1
±4
±1
±4
±1
±3
±3
AD5371