EVAL-AD5371EBZ Analog Devices Inc, EVAL-AD5371EBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD5371EBZ
• Description: BOARD EVAL FOR AD5371
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5371EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5371
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5371
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5371 contains 40 DAC channels and 40 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 14-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, of equal value, from VREFx to AGND. This type of
architecture guarantees DAC monotonicity. The 14-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
Table 8. Register Descriptions
Register
Name
X1A
X1B
M
C
X2A
X2B
DAC
OFS0
OFS1
OFS2
Control
A/B Select 0
A/B Select 1
A/B Select 2
A/B Select 3
A/B Select 4
Word
Length
(Bits)
14
14
14
14
14
14
14
14
14
3
8
8
8
8
8
Default
Value
0x1555
0x1555
0x3FFF
0x2000
Not user
accessible
Not user
accessible
Not user
accessible
0x1555
0x1555
0x1555
0x00
0x00
0x00
0x00
0x00
0x00
Description
Input Data Register A. One for each DAC channel.
Input Data Register B. One for each DAC channel.
Gain trim registers. One for each DAC channel.
Offset trim registers. One for each DAC channel.
Output Data Register A. One for each DAC channel. These registers store the final, calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
Output Data Register B. One for each DAC channel. These registers store the final, calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.
Data registers from which the DACs take their final input data. The DAC registers are updated from
the X2A or X2B register. They are not readable or directly writable.
Offset DAC 0 data register. Sets offset for Group 0.
Offset DAC 1 data register. Sets offset for Group 1.
Offset DAC 2 data register. Sets offset for Group 2 to Group 4.
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = global selection of X1B input data registers.
Bit 1 = enable thermal shutdown.
0 = disable thermal shutdown.
1 = enable thermal shutdown.
Bit 0 = software power-down.
0 = software power-up.
1 = software power-down.
Each bit in this register determines if a DAC in Group 0 takes its data from Register X2A or Register X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC in Group 1 takes its data from Register X2A or Register X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC in Group 2 takes its data from Register X2A or Register X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC in Group 3 takes its data from Register X2A or Register X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC in Group 4 takes its data from Register X2A or Register X2B.
0 = X2A.
1 = X2B.
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output voltage by 4. The nominal output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 40 DAC channels of the AD5371 are arranged into five
groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. The eight DACs of Group 1
derive their reference voltage from VREF1. Group 2 to Group 4
derive their reference voltage from VREF2. Each group has its
own signal ground pin.