EVAL-AD5371EBZ Analog Devices Inc, EVAL-AD5371EBZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD5371EBZ
• Description: BOARD EVAL FOR AD5371
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5371EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5371
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or the X1B input
register, depending on the setting of the A /B bit in the control
register. If the A /B bit is 0, data is written to the X1A register.
If the A /B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per-
channel basis so that some writes are to X1A registers and
some writes are to X1B registers.
Each DAC channel also has a gain (M) register and an offset (C)
register that allow trimming out of the gain and offset errors of
the entire signal chain. Data from the X1A register is operated
on by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
Although Figure 20 shows a multiplier and adder for each
channel, there is only one multiplier and one adder in the device
shared among all channels. This has implications for the update
speed when several channels are updated simultaneously, as
described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
register with the A /B control bit set to 0, the X2A data is recal-
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B, or to M or C
with A /B set to 1. The X2A and X2B registers are not readable
or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC 0 to DAC 7).
Note that because there are 40 bits in five registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B select registers to 0 or to 1.
REGISTER
REGISTER
REGISTER
REGISTER
Figure 20. Data Registers Associated with Each DAC Channel
X1A
X1B
M
C
MUX
REGISTER
REGISTER
X2A
X2B
MUX
REGISTER
DAC
DAC
Rev. B | Page 17 of 28
LOAD DAC
All DACs in the AD5371 can be updated simultaneously by
taking LDAC low when each DAC register is updated from
either its X2A or X2B register, depending on the setting of the
A/B select registers. The DAC register is not readable or directly
writable by the user. LDAC can be permanently tied low, and
the DAC output is updated whenever new data appears in the
appropriate DAC register.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
three 14-bit offset DACs, one for Group 0, one for Group 1, and
one for Group 2 to Group 4. These allow the output range of all
DACs connected to them to be offset within a defined range.
Thus, subject to the limitations of headroom, it is possible to set
the output range of Group 0, Group 1, or Group 2 to Group 4 to
be unipolar positive, unipolar negative, or bipolar, either symmet-
rical or asymmetrical about 0 V. The DACs in the AD5371 are
factory trimmed with the offset DACs set at their default values.
This results in optimum offset and gain performance for the
default output range and span.
When the output range is adjusted by changing the value of the
offset DAC, an extra offset is introduced due to the gain error of
the offset DAC. The amount of offset is dependent on the magni-
tude of the reference and how much the offset DAC deviates from
its default value. See the Specifications section for this offset. The
worst-case offset occurs when the offset DAC is at positive or
negative full scale. This value can be added to the offset present
in the main DAC channel to give an indication of the overall
offset for that channel. In most cases, the offset can be removed
by programming the C register of the channel with an appropriate
value. The extra offset caused by the offset DAC needs to be taken
into account only when the offset DAC is changed from its default
value. Figure 21 shows the allowable code range that can be loaded
to the offset DAC, depending on the reference value used. Thus,
for a 5 V reference, the offset DAC should not be programmed
with a value greater than 8192 (0x2000).
5
4
3
2
1
0
0
Figure 21. Offset DAC Code Range
4096
OFFSET DAC CODE
8192
12288
RESERVED
AD5371
16383