EVAL-AD5379EBZ Analog Devices Inc, EVAL-AD5379EBZ Datasheet - Page 3

BOARD EVALUATION FOR AD5379

EVAL-AD5379EBZ

Manufacturer Part Number
EVAL-AD5379EBZ
Description
BOARD EVALUATION FOR AD5379
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-AD5379EBZ

Number Of Dac's
40
Number Of Bits
14
Outputs And Type
40, Single Ended
Sampling Rate (per Second)
50k
Data Interface
Serial, Parallel
Settling Time
20µs
Dac Type
Voltage
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD5379
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
GENERAL DESCRIPTION
The AD5379 contains 40 14-bit DACs in one CSPBGA package.
The AD5379 provides a bipolar output range determined by the
voltages applied to the V
mum output voltage span is 17.5 V, corresponding to a bipolar
output range of −8.75 V to +8.75 V, and is achieved with reference
voltages of V
The AD5379 offers guaranteed operation over a wide V
supply range from ±11.4 V to ±16.5 V. The output amplifier
headroom requirement is 2.5 V operating with a load current of
1.5 mA, and 2 V operating with a load current of 0.5 mA.
The AD5379 contains a double-buffered parallel interface in
which 14 data bits are loaded into one of the input registers
Table 1. High Channel Count, Low Voltage, Single-Supply DACs
Model
AD5380BST-5
AD5380BST-3
AD5381BST-5
AD5381BST-3
AD5384BBC-5
AD5384BBC-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
REF
(−) = −3.5 V and V
Resolution
14 bits
14 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
12 bits
12 bits
12 bits
12 bits
14 bits
14 bits
14 bits
14 bits
REF
(+) and V
AV
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
REF
DD
REF
(+) = +5 V.
Range
(−) inputs. The maxi-
Output Channels
40
40
40
40
40
40
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
8
SS
/V
DD
Rev. B | Page 3 of 28
Linearity Error (LSB)
±4
±4
±1
±1
±4
±4
±4
±4
±1
±1
±3
±3
±4
±4
±1
±1
±1
±1
±3
±3
±4
±4
under the control of the WR , CS , and DAC Channel Address
Pins A0 to A7. It also has a 3-wire serial interface that is com-
patible with SPI®, QSPI™, MICROWIRE™, and DSP® interface
standards and can handle clock speeds of up to 50 MHz.
The DAC outputs are updated upon reception of new data into
the DAC registers. All the outputs can be simultaneously updated
by taking the LDAC input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external REFGND input. The DAC outputs can also be
switched to REFGND via the CLR pin.
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package Option
ST-100
ST-100
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
AD5379

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