EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7723CBZ
• Description: BOARD EVALUATION FOR AD7723
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7723CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 475mW @ 1.2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7723
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7723
In all cases, since the REF2 voltage connects to the analog
modulator, a 220 nF and 10 nF capacitor must connect directly
from REF2 to AGND. The external capacitor provides the
charge required for the dynamic load presented at the REF2 pin
(see Figure 41).
The AD780 is ideal to use as an external reference with the
AD7723. Figure 42 shows a suggested connection diagram.
Grounding Pin 8 on the AD780 selects the 3 V output mode.
1µ F
CLOCK GENERATION
The AD7723 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with a crystal is shown
in Figure 43. Consult the manufacturer’s recommendation for
the load capacitors. To enable the oscillator circuit on board the
AD7723, XTAL_OFF should be tied low.
5V
22nF
220nF
Figure 42. External Reference Circuit Connection
10nF
NC = NO CONNECT
1
2
3
4
REF2
Figure 41. REF2 Equivalent Input Circuit
NC
+V
TEMP
GND
IN
AD780
23
SELECT
TRIM
V
OUT
O/P
CLKIN
NC
8
7
6
5
Φ
Φ
22µ F
Φ
220nF
2.5V
A
A
B
Φ
SWITCHED-CAP
DAC REFERENCED
4pF
4pF
B

Φ
A
10nF
Φ
Φ
Φ
B
B
A
REF2
REF1
AD7723
Rev. C | Page 22 of 32
When an external clock source is being used, the internal
oscillator circuit can be disabled by tying XTAL_OFF high. A
low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively
modulates the input signal and raises the noise floor. The
sampling clock generator should be isolated from noisy digital
circuits, grounded, and heavily decoupled to the analog ground
plane.
The sampling clock generator should be referenced to the
analog ground in a split ground system. However, this is not
always possible because of system constraints. In many
applications, the sampling clock must be derived from a higher
frequency multipurpose system clock that is generated on the
digital ground plane. If the clock signal is passed between its
origin on a digital ground plane to the AD7723 on the analog
ground plane, the ground noise between the two planes adds
directly to the clock and produces excess jitter. The jitter can
cause degradation in the signal-to-noise ratio and also produce
unwanted harmonics. This can be remedied somewhat by
transmitting the sampling signal as a differential one, using
either a small RF transformer or a high speed differential driver
and a receiver such as PECL. In either case, the original master
system clock should be generated from a low phase noise crystal
oscillator.
Figure 43. Crystal Oscillator Connection
XTAL
AD7723
1MΩ
CLKIN