EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet
EVAL-AD7723CBZ
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EVAL-AD7723CBZ Summary of contents
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FEATURES 16-bit Σ-∆ ADC 1.2 MSPS output word rate 32×/16× oversampling ratio Low-pass and band-pass digital filter Linear phase On-chip 2.5 V voltage reference Standby mode Flexible parallel or serial interface Crystal oscillator Single 5 V supply GENERAL DESCRIPTION The ...
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AD7723 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Specifications....................................................................... 6 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration And Function Descriptions.......................... 11 Terminology .................................................................................... 14 Typical Performance Characteristics ........................................... 15 Circuit Description......................................................................... 18 Applying the AD7723 .................................................................... 20 Analog Input ...
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SPECIFICATIONS ± 5%; AGND = AGND1 = AGND2 = DGND = otherwise noted. Table 1. Parameter 2, 3 DYNAMIC SPECIFICATIONS Decimate by 32 Bipolar Mode Signal to Noise ...
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AD7723 Parameter Low-Pass Decimate kHz to f /41.75 CLKIN f /33.45 CLKIN f /32 CLKIN f /25. CLKIN CLKIN Group Delay Settling Time Band-Pass Decimate /51. /41.75 CLKIN CLKIN ...
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Parameter LOGIC OUPUTS V , Output High Voltage Output Low Voltage OL POWER SUPPLIES AVDD DVDD 6 Power Consumption 1 Operating temperature range is −40°C to +85°C (B: Version). 2 Typical ...
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AD7723 TIMING SPECIFICATIONS ± 5%; AGND = AGND1 = DGND = high unless otherwise noted. A MIN MAX Table 2. Parameter CLKIN ...
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CLKIN 0. FSI SCO Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output CLKIN t 8 FSI (SFMT = SCO (CFMT = ...
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AD7723 CLKIN t 8 FSI t 14 SCO (CFMT = FSO D15 D14 SDO D2 D1 Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and ...
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CLKIN DRDY t 20 DB0–DB15 WORD N – 1 Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low CLKIN DRDY t 22 RD/ DB0–DB15 CLKIN t 26 SYNC t 25 DRDY ...
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AD7723 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter Rating DV to DGND −0 AGND −0 DD1 ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND/DB2 DGND/DB1 DGND/DB0 DGND/DRDY Table 6. Pin Function Descriptions Pin No. Mnemonic Description 6, 28 DGND Ground Reference for Digital Circuitry MODE1/MODE2 Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel ...
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AD7723 Pin No. Mnemonic Description 29 SYNC Synchronization Logic Input. When using more than one AD7723 operated from a common master clock, SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising edge ...
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Table 8. Serial Mode Pin Function Descriptions Pin No. Mnemonic Description 1 DGND/DB2 Tie to DGND. 2 DGND/DB1 Tie to DGND. 3 DGND/DB0 Tie to DGND. 4 CFMT/RD Serial Clock Format Logic Input. The clock format pin selects whether the ...
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... Noise is the rms sum of all of the nonfundamental signals up to half the output data rate (F /2), excluding dc. The ADC is O evaluated by applying a low noise, low distortion sine wave signal to the input pins. By generating a fast fourier transform (FFT) plot, the SNR data can then be obtained from the output spectrum. ...
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TYPICAL PERFORMANCE CHARACTERISTICS 25°C; CLKIN = 19.2 MHz; external 2.5 V reference, unless otherwise noted 110 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz 100 90 THD 80 SFDR ...
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AD7723 2000 V (+) = V (– 1800 8192 SAMPLES TAKEN 1600 1400 1200 1000 800 600 400 200 0 32700 32702 32704 32706 32708 CODE Figure 18. Histogram of Output Codes with DC Input (Output Data Rate ...
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AI (HALF_POWER = 0) DD 175 150 125 100 AI (HALF_POWER = CLOCK FREQUENCY (MHz) Figure 24. Power Consumption vs. CLKIN Frequency 0 SNR = –86.19dB ...
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AD7723 CIRCUIT DESCRIPTION The AD7723 ADC employs a Σ-Δ conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, f Due ...
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CLKIN Figure 29. Low-Pass Filter Decimate by 16 0dB –100dB 0 0.5 f CLKIN Figure 30. Low-Pass Filter Decimate by 32 0dB –100dB 0 0.5 f CLKIN Figure 31. Band-Pass Filter Decimate by 32 Figure ...
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AD7723 APPLYING THE AD7723 ANALOG INPUT RANGE The AD7723 has differential inputs to provide common-mode noise rejection. In unipolar mode, the analog input range 8/5 × while in bipolar mode, the analog input range is ...
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Figure 37. Input RC Network With the unipolar input mode selected, just one op amp is required to buffer single-ended input signals. However, driving the AD7723 with complementary signals and with the bipolar input range selected has ...
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AD7723 In all cases, since the REF2 voltage connects to the analog modulator, a 220 nF and 10 nF capacitor must connect directly from REF2 to AGND. The external capacitor provides the charge required for the dynamic load presented at ...
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SYSTEM SYNCHRONIZATION The SYNC input provides a synchronization function for use in parallel or serial mode. SYNC allows the user to begin gathering samples of the analog input from a known point in time. This allows a system using multiple ...
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AD7723 DATA INTERFACING The AD7723 offers a choice of serial or parallel data interface options to meet the requirements of a variety of system configurations. In parallel mode, multiple AD7723s can easily be configured to share a common data bus. ...
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SERIAL INTERFACE The AD7723’s serial data interface can operate in three modes, depending on the application requirements. The timing diagrams in Figure 4, Figure 5, and Figure 6 show how the AD7723 may be used to transmit its conversion results. ...
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AD7723 The master device is selected by setting TSI to a logic low and connecting its FSO to DOE. The slave device is selected with its TSI pin tied high and both its FSI and DOE controlled from the master’s ...
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SERIAL INTERFACE TO DSPs In serial mode, the AD7723 can be directly interfaced to several industry-standard digital signal processors. In all cases, the AD7723 operates as the master with the DSP operating as the slave. The AD7723 provides its own ...
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AD7723 GROUNDING AND LAYOUT The analog and digital power supplies to the AD7723 are independent and separately pinned out to minimize coupling between the analog and digital sections within the device. The AD7723 AGND and DGND pins should be soldered ...
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... Figure 51. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters Package Description 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) 44-Lead Metric Quad Flat Package (MQFP) Evaluation Board Rev Page 13.90 BSC 10.00 BSC SQ ...
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AD7723 NOTES Rev Page ...
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NOTES Rev Page AD7723 ...
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AD7723 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01186–0–5/05(C) Rev Page ...