EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD7723CBZ
• Description: BOARD EVALUATION FOR AD7723
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7723CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 475mW @ 1.2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7723
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7723
Pin No.
29
39
Table 7. Parallel Mode Pin Function Descriptions
Pin
No.
1
2
3
4
5
30
31
32
33
34
35
36
37
38
40
41
42
43
44
Mnemonic
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/RD
DGND/DRDY
DV
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
DGND/DB3
DD
/CS
Mnemonic
SYNC
DV
DD
Description
Data Output Bit.
Data Output Bit.
Data Output Bit (LSB).
Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data bus is enabled
when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output
data bits, DB15 to DB0, are high impedance.
Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data
register. DRDY returns high upon completion of a read operation. If a read operation does not occur between output
updates, DRDY pulses high for two CLKIN cycles before the next output update. DRDY also indicates when
conversion results are available after a SYNC sequence.
Chip Select Logic Input.
Data Output Bit (MSB).
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Description
Synchronization Logic Input. When using more than one AD7723 operated from a common master clock,
SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising
edge resets the AD7723 digital filter sequencer counter to 0. When the rising edge of CLKIN senses a logic
low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset
during this action, SYNC pulses cannot be applied continuously.
Digital Power Supply Voltage; 5 V ± 5%.
Rev. C | Page 12 of 32