MAX7456EVKIT+ Maxim Integrated Products, MAX7456EVKIT+ Datasheet - Page 12

• Manufacturer Part Number: MAX7456EVKIT+
• Description: KIT EVAL FOR MAX7456
• Manufacturer: Maxim Integrated Products

Specifications of MAX7456EVKIT+

• Main Purpose: Video, On-Screen Display (OSD)
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: MAX7456
• Primary Attributes: NTSC/PAL single-channel monochrome on-screen display(OSD) with integrated video driver
• Secondary Attributes: GUI, SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The video timing generator is a digital circuit generat-
ing all internal and external (VSYNC and HSYNC) tim-
ing signals. VSYNC and HSYNC can be synchronized
to VIN, or run independently of any input when in inter-
nal sync mode. The video timing generator can gener-
ate NTSC or PAL timing using the same 27MHz crystal
(see Figures 4–9).
The internal crystal oscillator generates the system
clock used by the video timing generator. The oscillator
uses a 27MHz crystal or can be driven by an external
27MHz TTL clock at CLKIN. For external clock mode,
connect the 27MHz TTL input clock to CLKIN and leave
XFB unconnected.
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Figure 4. VOUT, VSYNC, and HSYNC Timing (NTSC, External Sync Mode)
12
(EVEN FIELD)
(EVEN FIELD)
(ODD FIELD)
(ODD FIELD)
______________________________________________________________________________________
VSYNC
HSYNC
HSYNC
VOUT
VOUT
Video Timing Generator
Crystal Oscillator
50%
50%
50%
VERTICAL SYNCHRONIZATION
t
VOUT-VSF
The display memory stores 480 character addresses
that point to the characters stored in the NVM character
memory. The content of the display memory is user-
programmable through the SPI-compatible serial inter-
face. The display-memory address corresponds to a
fixed location on a monitor (see Figure 10). Momentary
breakup of the OSD image can be prevented by writing
to the display memory during the vertical blanking inter-
val. This can be achieved by using VSYNC as an inter-
rupt to the host processor to initiate writing to the
display memory.
PULSE INTERVAL
50%
50%
Display Memory (SRAM)
t
VOUT-VSR
1/2H