SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 66
![BOARD EVAL FOR SI5325/26](/photos/28/95/289557/si5325_sml.jpg)
SI5325/26-EVB
Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Specifications of SI5325/26-EVB
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si5326
9. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5326. Table 11 lists the values for the dimensions shown in the
illustration.
66
Notes:
Symbol
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
A1
D2
E2
D
A
b
e
E
Components.
0.80
0.00
0.18
3.95
3.95
Min
Millimeters
6.00 BSC
0.50 BSC
6.00 BSC
Nom
0.85
0.02
0.25
4.10
4.10
Figure 7. 36-Pin Quad Flat No-lead (QFN)
Table 11. Package Dimensions
Max
0.90
0.05
0.30
4.25
4.25
Rev. 1.0
Symbol
aaa
bbb
ddd
eee
ccc
L
0.50
Min
—
—
—
—
—
—
Millimeters
Nom
0.60
—
—
—
—
—
—
Max
0.70
0.10
0.10
0.08
0.10
0.05
12º