SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 37
![BOARD EVAL FOR SI5325/26](/photos/28/95/289557/si5325_sml.jpg)
SI5325/26-EVB
Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Specifications of SI5325/26-EVB
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Reset value = 0011 1111
Register 24.
Name
Type
7:3
Bit
Bit
2
1
0
FOS2_MSK
FOS1_MSK
LOL_MSK
Reserved
Name
D7
Reserved.
FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
LOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-
ter do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOL_FLG ignored in generating interrupt output.
D6
Reserved
D5
R
Rev. 1.0
D4
Function
D3
FOS2_
MSK
R/W
D2
FOS1_
MSK
R/W
D1
Si5326
LOL_MSK
R/W
D0
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