SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 30
![BOARD EVAL FOR SI5325/26](/photos/28/95/289557/si5325_sml.jpg)
SI5325/26-EVB
Manufacturer Part Number
SI5325/26-EVB
Description
BOARD EVAL FOR SI5325/26
Manufacturer
Silicon Laboratories Inc
Specifications of SI5325/26-EVB
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5325, SI5326
Processor To Be Evaluated
Si5325 and Si5326
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si5326
Reset value = 0100 0000
Reset value = 0000 0000
30
Register 11.
Register 16.
Name
Name
Type
Type
7:2
7:0
Bit
Bit
Bit
Bit
1
0
CLAT [7:0]
Reserved
PD_CK2
PD_CK1
Name
Name
D7
D7
Reserved.
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
CLAT [7:0].
With INCDEC_PIN = 0, this register sets the phase delay for CKOUTn in units of
1/Fosc. This can take as long as 20 seconds.
01111111 = 127/Fosc (2s compliment)
00000000 = 0
10000000 = -128/Fosc (2s compliment)
If NI_HS[2:0] = 000, increasing CLAT does not work.
D6
D6
D5
D5
Reserved
R
Rev. 1.0
D4
D4
CLAT [7:0]
R/W
Function
Function
D3
D3
D2
D2
PD_CK2
R/W
D1
D1
PD_CK1
R/W
D0
D0