SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 31

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset value = 1000 0000
Reset value = 0000 0000
Register 17.
Register 18.
Name
Name
Type
Type
6:0
7:0
Bit
Bit
Bit
Bit
7
FLAT_VALID FLAT_VALID.
FLAT [14:8]
FLAT [7:0]
FLAT_
VALID
R/W
Name
Name
D7
D7
Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the
existing FLAT[14:0] value to be held internally for use while the new value is being writ-
ten. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to enable
its use.
0: Memorize existing FLAT[14:0] value and ignore intermediate register values during
write of new FLAT[14:0] value.
1: Use FLAT[14:0] value directly from registers.
FLAT [14:8].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
FLAT [7:0].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
D6
D6
D5
D5
Rev. 1.0
D4
D4
FLAT [7:0]
R/W
FLAT [14:8]
Function
Function
R/W
D3
D3
D2
D2
D1
D1
Si5326
D0
D0
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