SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet - Page 54

• Manufacturer Part Number: SI5325/26-EVB
• Description: BOARD EVAL FOR SI5325/26
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5325/26-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5325, SI5326
• Processor To Be Evaluated: Si5325 and Si5326
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5326
Reset value = 0000 0000
54
Register 136.
Name
Type
5:0
Bit
Bit
7
6
RST_REG
RST_REG
Reserved
R/W
Name
D7
ICAL
Internal Reset (Same as Pin Reset).
Note: The I
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a “1” to this location initiates an ICAL. The calibration is com-
plete once the LOL alarm goes low.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-
tion, LOL will go low.
Notes:
Reserved.
ICAL
R/W
D6
1. A valid stable clock (within 100 ppm) must be present to begin ICAL.
2. If the input changes by more than 500 ppm, the part may do an autonomous ICAL.
3. See Table 9, “Register Locations Requiring ICAL,” on page 63 for register changes that
require an ICAL.
2
C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
D5
Rev. 1.0
D4
Function
D3
Reserved
R
D2
D1
D0