LMK03200EVAL National Semiconductor, LMK03200EVAL Datasheet - Page 29

• Manufacturer Part Number: LMK03200EVAL
• Description: BOARD EVALUATION LMK03200
• Manufacturer: National Semiconductor

Specifications of LMK03200EVAL

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK03200
• Primary Attributes: 3 LVDS & 5 LVPECL Outputs, Integrated PLL & VCO
• Secondary Attributes: 3.15 V ~ 3.45 V Supply
• Silicon Manufacturer: National
• Silicon Core Number: LMK03200
• Kit Application Type: Clock & Timing
• Application Sub Type: Precision Clock Conditioner
• Kit Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL phase detector. Since the VCO Divider is also in the
feedback path from the VCO to the PLL Phase Detector, the
total N divide value, N
vider value. N
frequency is calculated as, f
VCO Divider / PLL R Divider. Since the PLL N divider is a pure
binary counter there are no illegal divide values for PLL_N
[17:0] except for 0.
2.10.2 VCO_DIV [3:0] -- VCO Divider
These bits program the divide value for the VCO Divider. The
VCO Divider follows the VCO output and precedes the clock
distribution blocks. Since the VCO Divider is in the feedback
path from the VCO to the PLL phase detector the VCO Divider
contributes to the total N divide value, N
Divider × VCO Divider. The VCO Divider can not be by-
passed. See the programming section on the PLL N Divider
for more information on setting the VCO frequency.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
0
0
0
0
0
0
0
0
1
1
1
.
VCO_DIV [3:0]
Total
0
0
0
0
1
1
1
1
0
0
1
.
PLL_N [17:0]
= PLL N Divider × VCO Divider. The VCO
Total
0
0
1
1
0
0
1
1
0
0
1
.
, is also influenced by the VCO Di-
VCO
= f
0
1
0
1
0
1
0
1
0
1
1
.
OSCin
Total
× PLL N Divider ×
VCO Divider
. N
2 (default)
Invalid
Invalid
Invalid
Invalid
Value
Total
...
(default)
3
4
5
6
7
8
Divider
262143
PLL N
Invalid
Value
760
= PLL N
...
...
1
29
2.10.3 PLL_CP_GAIN [1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
PLL_CP_GAIN [1:0]
0
1
2
3
Charge Pump Gain
1x (default)
16x
32x
4x
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