STEVAL-ISQ002V1 STMicroelectronics, STEVAL-ISQ002V1 Datasheet - Page 113
![BOARD EVAL BASED ON ST72264G1](/photos/9/9/90917/steval-isq002v1_sml.jpg)
STEVAL-ISQ002V1
Manufacturer Part Number
STEVAL-ISQ002V1
Description
BOARD EVAL BASED ON ST72264G1
Manufacturer
STMicroelectronics
Specifications of STEVAL-ISQ002V1
Main Purpose
Interface, PMBus
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F264
Primary Attributes
The PMBus™ Interface Using the ST7 I2C Peripheral
Secondary Attributes
Firmware in C Language
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6423
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
STEVAL-ISQ002V1
Manufacturer:
STMicroelectronics
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1
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I
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I
1: Fast I
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I
when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for
the table of values.
Note: The programmed F
SCL and SDA lines.
FM/SM
2
2
C BUS INTERFACE (Cont’d)
C CLOCK CONTROL REGISTER (CCR)
7
CC6
2
C mode
2
CC5
C mode
2
C mode. They are not cleared
CC4
SCL
CC3
assumes no load on
2
C mode.
CC2
CC1
SCL
CC0
) de-
0
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
– Transmitter mode: Byte transmission start auto-
– Receiver mode: the first data byte is received au-
2
C DATA REGISTER (DR)
matically when the software writes in the DR reg-
ister.
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
D7
7
ST72260Gx, ST72262Gx, ST72264Gx
D6
D5
D4
D3
D2
D1
113/172
D0
0
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