ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 35

• Manufacturer Part Number: ADV212-HD-EB
• Description: BOARD EVALUATION FOR ADV212-HD
• Manufacturer: Analog Devices Inc

Specifications of ADV212-HD-EB

• Main Purpose: Video, Video Processing
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADV212-HD
• Primary Attributes: 1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
• Secondary Attributes: GUI, JPEG2000 Video Codec
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM5 pin is connected to the same GPIO on the host.
32-BIT HOST CPU
DATA[31:0]
ADDR[3:0]
DREQ
DACK
DREQ
DACK
GPIO
ACK
ACK
IRQ
IRQ
WR
WR
CS
RD
CS
RD
Figure 34. Decode—Multichip Master/Slave Application
ADV212_1_MASTER
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
ADV212_2_SLAVE
VDATA[11:2]
VDATA[11:2]
Rev. B | Page 35 of 44
HSYNC
HSYNC
VSYNC
VSYNC
MCLK
FIELD
MCLK
FIELD
VCLK
VCLK
Y
CbCr
In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync, and each
SCOMM5 is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
74.25MHz
OSC
CbCr
Y
CLKIN
Y[9:0]
C[9:0]
10-BIT SD/HD
ENCODER
VIDEO
1080i
VIDEO OUT
ADV212