ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 15

• Manufacturer Part Number: ADV212-HD-EB
• Description: BOARD EVALUATION FOR ADV212-HD
• Manufacturer: Analog Devices Inc

Specifications of ADV212-HD-EB

• Main Purpose: Video, Video Processing
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADV212-HD
• Primary Attributes: 1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
• Secondary Attributes: GUI, JPEG2000 Video Codec
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

VDATA MODE TIMING
Table 11.
Parameter
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
Decode Slave Data Sync Delay
Decode Slave Data Sync Delay
1
The sync delay value varies according to the application.
(HSYNC Low to First 0xFF of EAV/SAV Code)
(HSYNC Low to First Data for HVF Mode)
VDATA (IN)
VDATA (IN)
VSYNC
FIELD
VCLK
HSYNC
VCLK
VCLK
Cr
FIELD
SU
Y
VDATA
Cb
SU
Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing)
Y
Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing)
FF
VDATA
Figure 21. Encode Video Mode Timing—CCIR 656 Mode
VSYNC
(VSYNC and FIELD Programmed for Negative Polarity)
00
HSYNC
HD
(HSYNC Programmed for Negative Polarity)
SU
SU
00
Rev. B | Page 15 of 44
EAV
Cb
VDATA
VDATA
HSYNC
VSYNC
VSYNC
FIELD
FIELD
SYNC DELAY
Mnemonic
VDATA
HSYNC
HSYNC
VSYNC
FIELD
FF
SU
HD
TD
TD
SU
HD
SU
HD
TD
SU
HD
TD
Y
00
VSYNC
Cr
00
HD
Y
Min
4
4
3
4
3
4
4
3
SAV
HSYNC
Cb
FIELD
HD
Cb
HD
Typ
8
10
1
Y
1
Y
Cr
Max
12
12
12
12
Cr
Y
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCLK cycles
VCLK cycles
ADV212