ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 10

• Manufacturer Part Number: ADV212-HD-EB
• Description: BOARD EVALUATION FOR ADV212-HD
• Manufacturer: Analog Devices Inc

Specifications of ADV212-HD-EB

• Main Purpose: Video, Video Processing
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADV212-HD
• Primary Attributes: 1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
• Secondary Attributes: GUI, JPEG2000 Video Codec
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV212
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
RD to DACK Setup
DACK to Data Valid
Data Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold after DACK Deassert
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
1
For a definition of JCLK, see Figure 32.
HDATA
HDATA
DREQ
DACK
DREQ
DACK
RD
RD
DREQ
t
t
Figure 10. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
RD
Figure 9. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
RD
SU
SU
PULSE
(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)
DACK
DACK
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
t
t
RD
RD
LOW
LOW
t
t
DREQ
DREQ
0
0
DACK
DACK
RTN
t
t
HIGH
HIGH
HD
HD
Rev. B | Page 10 of 44
Mnemonic
DREQ
t
t
t
t
DACK
DACK
t
RDFSRQ
t
DREQ
RD SU
RD
HD
RD HD
DREQ RTN
PULSE
LOW
HIGH
1
1
Min
1 JCLK
2.5 JCLK
0
2.5
1.5
2 JCLK
2 JCLK
0
1.5 JCLK
2.5 JCLK
1
1
1
1
1
1
2
2
Typ
t
t
RD
RD
HD
HD
Max
15 JCLK
3.5 × JCLK + 9.0
11
2.5 × JCLK + 9.0
3.5 × JCLK + 9.0
1
1
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns