CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 48

• Manufacturer Part Number: CDB42428
• Description: BOARD EVAL FOR CS42428 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42428

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42428/26/18/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1499

48
6.7
6.7.1
6.7.2
6.7.3
RMCK_DIV1
7
Clock Control (address 06h)
RMCK DIVIDE (RMCK_DIVX)
OMCK FREQUENCY (OMCK FREQX)
PLL LOCK TO LRCK (PLL_LRCK)
Default = 00
Function:
Default = 00
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42428 will lock to the ADC_LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in Slave Mode.
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
Sets the appropriate frequency for the supplied OMCK.
RMCK_DIV0
OMCK Freq1 OMCK Freq0
6
0
0
1
1
OMCK Freq1
RMCK_DIV1 RMCK_DIV0
5
0
0
1
1
Table 10. OMCK Frequency Settings
0
1
0
1
Table 9. RMCK Divider Settings
OMCK Freq0
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
4
0
1
0
1
PLL_LRCK
Description
Multiply by 2
Divide by 1
Divide by 2
Divide by 4
3
Description
SW_CTRL1
2
SW_CTRL0
1
FRC_PLL_LK
CS42428
DS605F1
0