CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 43

• Manufacturer Part Number: CDB42428
• Description: BOARD EVAL FOR CS42428 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42428

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42428/26/18/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1499

DS605F1
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
DAC_FM1
Reserved
7
7
Power Control (address 02h)
POWER DOWN PLL (PDN_PLL)
POWER DOWN ADC (PDN_ADC)
POWER DOWN DAC PAIRS (PDN_DACX)
POWER DOWN (PDN)
Functional Mode (address 03h)
DAC FUNCTIONAL MODE (DAC_FMX)
Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP).
Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave Mode.
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 1
Function:
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
When enabled, the PLL is held in a reset state. It is advised that any change of this bit be made while
the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible
artifacts.
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
DAC_FM0
PDN_PLL
6
6
PDN_ADC
ADC_FM1
5
5
PDN_DAC4
ADC_FM0
4
4
PDN_DAC3
Reserved
3
3
ADC_SP SEL
PDN_DAC2
2
2
PDN_DAC1
DAC_DEM
1
1
CS42428
Reserved
PDN
0
0
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