CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 46

• Manufacturer Part Number: CDB42428
• Description: BOARD EVAL FOR CS42428 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42428

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42428/26/18/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1499

46
6.5.4
6.6
6.6.1
6.6.2
6.6.3
Ext ADC SCLK
7
CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)
Misc Control (address 05h)
EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)
RMCK HIGH IMPEDANCE (HIZ_RMCK)
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC. By de-
fault, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits.
0 - 24 bit mode.
1 - 16 bit mode.
This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using
One-Line Mode of operation.
0 - ADC_SCLK is used as external ADC SCLK.
1 - DAC_SCLK is used as external ADC SCLK.
This bit is used to create a high-impedance output on RMCK when the clock signal is not required.
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
HiZ_RMCK
6
Reserved
5
FREEZE
4
FILT_SEL
3
HPF_FREEZE
2
DAC_SP
M/S
1
CS42428
ADC_SP
DS605F1
M/S
0