CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 46

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

6.2.1. Intel Parallel Host
The Intel parallel host communication mode is
implemented using the pins given in
The INTREQ pin is controlled by the application
code when a parallel host communication mode
has been selected. When the code supports
INTREQ notification, the INTREQ pin is asserted
whenever the DSP has an outgoing message for
the host. This same information is reflected by the
HOUTRDY bit of the Host Control Register (A[1:0]
= 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP
without
Unsolicited messages can be used to notify the
host of conditions such as a change in the
incoming audio data type (e.g. PCM --> AC-3).
6.2.1.1. Writing a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Write Cycle are met.
46
Chip Select
Write Enable
Output Enable
Register Address Bit 1
Register Address Bit 0
Interrupt Request
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Table 6. Intel Mode Communication Signals
Mnemonic
Communication Mode
an
associated
CS
WR
RD
A1
A0
INTREQ
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Pin Name
host
read
Table
18
4
5
6
7
19
8
9
10
11
14
15
16
17
Pin Number
request.
6.
The flow diagram shown in
sequence of events that define a one-byte write in
Intel mode. The protocol presented in
will now be described in detail.
1) The host must first drive the A1 and A0 register
2) The host then indicates that the selected
3) The host drives the data byte to the DATA[7:0]
4) Once the setup time for the write has been met,
6.2.1.2. Reading a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Read Cycle are met.
Figure 24. Intel Mode, One-Byte Write Flow Dia-
address pins of the CS493XX with the address
of the desired Parallel I/O Register.
Host Message:
Host Control:
PCMDATA:
CMPDATA:
register will be written. The host initiates a write
cycle by driving the CS and WR pins low.
pins of the CS493XX.
the host ends the write cycle by driving the CS
and WR pins high.
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
CS49300 Family DSP
WRITE BYTE TO
WR (HIGH)
DATA [7:0]
CS (HIGH)
WR (LOW)
CS (LOW)
Figure 24
A[1:0]==00b.
A[1:0]==01b.
A[1:0]==10b.
A[1:0]==11b.
illustrates the
Figure 24
DS339F7