CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 41

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

6) If INTREQ is still low after a byte transfer, an
DS339F7
the host is valid on the rising edge of SCCLK
and data transitions occur on the falling edge of
SCCLK.
acknowledge (SCDIO clocked low by SCCLK)
must be sent by the host to the CS493XX and
another byte should be clocked out of the
CS493XX. Please see the discussion below for
a complete description of INTREQ’s behavior.
RISING EDGE OF SCDIO
Figure 23. I
WRITE ADDRESS BYTE
WHILE SCCLK IS HIGH
INTREQ
SET TO 1 FOR READ
WHILE SCLK IS HIGH
DROP SCDIO LOW
SEND I
READ DATABYTE
SEND I
INTREQ
WITH MODE BIT
SEND NACK
GET ACK
STILL LOW?
2
2
C START:
C STOP:
2
LOW?
YES
NO
C
®
Read Flow Diagram
YES
NO
SEND ACK
7) When INTREQ has risen, a no acknowledge
Understanding the role of INTREQ is important for
successful communication. INTREQ is guaranteed
to remain low (once it has gone low), until the rising
edge of SCCLK for the last bit of the last byte to be
transferred out of the CS493XX (i.e. the rising
edge of SCCLK before the ACK SCCLK). If there
is no more data to be transferred, INTREQ will go
high at this point. After going high, INTREQ is
guaranteed to stay high until the next rising edge of
SCCLK (i.e. it will stay high until the rising edge of
SCCLK for the ACK/NACK bit). This end of transfer
condition signals the host to end the read
transaction by clocking the last data bit out of the
CS493XX and then sending a no acknowledge to
the CS493XX to signal that the read sequence is
over. At this point the host should send an I
stop condition to complete the read sequence. If
INTREQ is still low after the rising edge of SCCLK
on the last data bit of the current byte, the host
should send an acknowledge and continue reading
data from the serial control port.
It should be noted that all data should be read out
of the serial control port during one cycle or a loss
of data will occur. In other words, all data should be
read out of the chip until INTREQ signals the last
byte by going high as described above. Please see
Section 6.1.3, “INTREQ Behavior: A Special Case”
on page 41
INTREQ behavior.
The timing diagram in
page 42
lines for an I
6.1.3. INTREQ Behavior: A Special
When communicating with the CS493XX there are
two types of messages which force INTREQ to go
low. These messages are known as solicited
messages and unsolicited messages. For more
information on the specific types of messages that
require a read from the host, one of the application
code user’s guides should be referenced.
should be sent by the host (SCDIO clocked
high by the host) to the CS493XX. This,
followed by an I
raised, while SCCLK is high) signals an end of
read to the CS493XX.
Case
shows the relative edges of the control
2
C
for a more detailed description of
®
read and write.
CS49300 Family DSP
2
Figure 24, "I2C® Timing" on
C
®
stop condition (SCDIO
2
C
41
®