Z8FMC160100KIT Zilog, Z8FMC160100KIT Datasheet - Page 200
Z8FMC160100KIT
Manufacturer Part Number
Z8FMC160100KIT
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KIT.pdf
(20 pages)
Specifications of Z8FMC160100KIT
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphic User Interface
Processor To Be Evaluated
Z8FMC16100
Data Bus Width
8 bit
Interface Type
USB
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3639
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Table 98. I
Table 99. I2CSTATE_H
BITS
FIELD
RESET
R/W
ADDR
PS024613-0910
State
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
2
C State Register (I2CSTATE) - Description when DIAG = 1
R
7
0
State Name
Idle
Slave Start
Slave Bystander
Slave Wait
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Slave Transmit Data
Slave Receive Data
Slave Receive Addr1
BUSY—I
0 = No activity on the I
1 = A transaction is underway on the I
I2CSTATE_H—I
This field defines the current state of the I
the internal state machine.
I2CSTATE_L—Least significant nibble of the I
substates for the states defined by I2CSTATE_H.
field.
2
C Bus Busy
R
6
I2CSTATE_H
0
2
C State
R
2
5
0
State Description
I
I
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
Master completing STOP condition (SCL = 1, SDA = 1).
MASTER mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
9 substates, one for each data bit and one for the Acknowledge.
9 substates, one for each data bit and one for the Acknowledge.
Slave receiving first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
C Bus.
2
2
C bus is idle or I
C controller has received a START condition.
Table 99
R
4
0
defines the states for this field.
2
C bus.
F55H
2
2
C Controller. It is the most significant nibble of
C controller is disabled.
R
3
0
2
C state machine. This field defines the
Table 100
Z8FMC16100 Series Flash MCU
R
2
0
I2CSTATE_L
defines the values for this
Product Specification
R
1
0
I
2
C State Register
R
0
0
188
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