MT9VDVF6472Y-335D4 Micron Technology Inc, MT9VDVF6472Y-335D4 Datasheet - Page 25

• Manufacturer Part Number: MT9VDVF6472Y-335D4
• Description: MODULE DDR 512MB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9VDVF6472Y-335D4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Package Type: VLP DIMM
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef81cf6969/Source: 09005aef81cf67b0
DVF9C32_64x72_2.fm - Rev. A 8/05 EN
23. Each byte lane as a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
25. To maintain a valid level, the transitioning edge of the input must:
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1 V/ns (2 V/ns differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
28. V
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
30.
31. READs and WRITEs with auto precharge are not allowed to be issued until
32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not
33. Normal Output Drive Curves:
34. The voltage levels used are derived from a minimum V
35. V
36. V
37.
during REFRESH command period (
standby).
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be
added to
V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.
the same amount.
t
device CK and CK# inputs, collectively during bank active.
can be satisfied prior to the internal precharge command being issued.
more than +400mV (2.9V max), whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed -300mV (2.2V min), whichever is more pos-
itive. However, the DC average cannot be below 2.3V minimum.
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
not be greater than 1/3 of the cycle rate. V
width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
t
prevail over
b. Reach at least the target AC level.
b. The variation in driver pull-down current within nominal limits of voltage and
d. The variation in driver pull-up current within nominal limits of voltage and tem-
a. Sustain a constant slew rate from the current AC level through to the target AC
a. The full variation in driver pull-down current from minimum to maximum pro-
e. The full variation in the ratio of the maximum to minimum pull-up and pull-
c. After the AC target level is reached, continue to maintain at least the target DC
c. The full variation in driver pull-up current from minimum to maximum process,
HP min is the lesser of
f. The full variation in the ratio of the nominal pull-up to pull-down current should
HZ (MAX) will prevail over
DD
IH
DD
overshoot: V
level, V
level, V
cess, temperature and voltage will lie within the outer bounding lines of the V-I
curve of Figure 8, "Pull-Down Characteristics," on page 26.
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, "Pull-Down Characteristics," on page 26.
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure 9, "Pull-Up Characteristics," on page 26.
perature is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 9, "Pull-Up Characteristics," on page 26.
down current should be between 0.71 and 1.4, for device drain-to-source voltages
from 0.1V to 1.0V, and at the same voltage and temperature.
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
must not vary more than 4 percent if CKE is not active while any bank is active.
and V
t
DS and
DD
IL
IL
t
(AC) or V
(DC) or V
DQSCK (MIN) +
Q must track each other.
IH
t
(MAX) = V
DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4
256MB, 512MB: (x72, SR) 184-Pin DDR VLP RDIMM
IH
IH
t
(AC).
CL minimum and
(DC).
25
t
DD
DQSCK (MAX) +
t
RPRE (MAX) condition.
Q + 1.5V for a pulse width ≤ 3ns and the pulse width can
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
IL
t
undershoot: V
CH minimum actually applied to the
t
RPST (MAX) condition.
DD
IL
level and the referenced test
(MIN) = -1.5V for a pulse
©2004 Micron Technology, Inc. All rights reserved.
t
LZ (MIN) will
t
RAS (MIN)
Notes