MT9VDVF6472Y-335D4 Micron Technology Inc, MT9VDVF6472Y-335D4 Datasheet
MT9VDVF6472Y-335D4
Specifications of MT9VDVF6472Y-335D4
Related parts for MT9VDVF6472Y-335D4
MT9VDVF6472Y-335D4 Summary of contents
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... Gold edge contacts PDF: 09005aef81cf6969/Source: 09005aef81cf67b0 DVF9C32_64x72_1.fm - Rev. A 8/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 256MB, 512MB: (x72, SR) 184-Pin DDR VLP RDIMM www.micron.com/modules Figure 1: 184-Pin VLP DIMM (MO-206) Very Low-Profile 0.72in. (18.29mm) Options • Operating temperature range Commercial (0° ...
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... MT9VDVF3272(I)Y-202__ 512MB MT9VDVF6472G-335__ MT9VDVF6472Y-335__ 512MB MT9VDVF6472G-262__ 512MB MT9VDVF6472Y-262__ 512MB 512MB MT9VDVF6472G-26A__ MT9VDVF6472Y-26A__ 512MB MT9VDVF6472(I)G-265__ 512MB MT9VDVF6472(I)Y-265__ 512MB 512MB MT9VDVF6472(I)G-202__ MT9VDVF6472(I)Y-202__ 512MB Note: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDVF3272-265B1. ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 184-Pin VLP DIMM (MO-206 ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Assignments and Descriptions Table 3: Pin Assignment 184-Pin DIMM Front Pin Symbol Pin Symbol Pin DQ17 47 REF 2 DQ0 25 DQS2 DQ1 ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol 10 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, 59 ...
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... V Supply Ground. SS Supply Serial EEPROM positive power supply: . DDSPD DNU — Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family NC — No Connect: These pins should be left unconnected. 8 Pin Assignments and Descriptions Description Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Unless otherwise noted, resistor values are 22Ω. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. Standard modules use the following DDR SDRAM devices: MT46V32M8FG (256MB) and MT46V64M8FG (512MB). Lead-free modules use the following DDR SDRAM devices: MT46V32M8BG (256MB) and MT46V64M8BG (512MB). ...
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... Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
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SDRAM organizations and timing parameters. The remaining 128 bytes of stor- age are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I bus ...
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Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ com- mand and the availability of the first bit of output data. The latency can be set 2.5 clocks, as ...
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Table 5: Burst Definition Table Burst Length Notes: 1. For A1–Ai select the two-data-element block; A0 selects the first access within the block. 2. For A2–Ai select the four-data-element block; A0–A1 select the first ...
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Figure 5: CAS Latency Diagram COMMAND COMMAND Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset ...
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The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any sub- sequent operation. Violating either of these requirements could result ...
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Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen- eral reference of available commands. For a more detailed description of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data ...
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Absolute Maximum Ratings Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
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Table 11: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 23–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 12: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 23–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 14: DDR Device Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1–5, 8, 10, 12; notes appear on pages 23–26; 0°C ≤ Characteristics Parameter Access window of DQs from CK/CK# CK high-level width CK low-level ...
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Table 14: DDR Device Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 23–26; 0°C ≤ Characteristics Parameter REFRESH to REFRESH command interval Average periodic refresh interval Terminating ...
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Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 23–26; 0°C ≤ Characteristics Parameter AUTO REFRESH command period ACTIVE to READ or WRITE ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output ...
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The intent of the Don’t Care state after completion of the postamble is that the DQS- driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input ...
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Each byte lane as a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( standby). 25. To maintain a valid level, the ...
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Figure 8: Pull-Down Characteristics 160 140 120 100 0.0 Figure 9: Pull-Up Characteristics 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0 t 38. RPST end point and but specify when the ...
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When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. 49. The -335 speed grade will operate with at any slower frequency. PDF: 09005aef81cf6969/Source: 09005aef81cf67b0 DVF9C32_64x72_2.fm - Rev. A 8/05 ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic LOW. 4. Provide stable clock signals. 5. Wait at ...
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Figure 10: Initialization Flow Diagram Step PDF: 09005aef81cf6969/Source: 09005aef81cf67b0 DVF9C32_64x72_2.fm - Rev. A 8/05 EN 256MB, 512MB: (x72, SR) ...
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PLL and Register Specifications Table 16: Register Timing Requirements and Switching Characteristics Note: 1 Register Symbol f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL t Pulse Duration w SSTL (bit pattern t ...
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Table 17: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 Parameter Symbol Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter t Half-Period Jitter Input Clock Slew ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 11, "Data Valid- ity," on page ...
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Figure 12: Definition of Start and Stop SCL SDA Figure 13: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef81cf6969/Source: 09005aef81cf67b0 DVF9C32_64x72_2.fm - Rev. A 8/05 EN 256MB, 512MB: (x72, SR) 184-Pin ...
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Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first Select Code Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes Mode Current Address Read Random Address Read Sequential Read ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA OUT Input Leakage Current: ...
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Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 30 Minimum RAS# Pulse Width, (See note 2) 31 Module Rank Density 32 Address and Command Setup Time, note 3) 33 Address and Command Hold ...
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... SR) 184-Pin DDR VLP RDIMM Entry (Version set to 7ns (0x70) for optimum BIOS compatibility. Actual device specifi- t RAS used for -26A/-265 modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 38 Serial Presence-Detect MT9VDVF3272 ...
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Package Dimensions All dimensions in inches (millimeters); Figure 15: 184-Pin VLP DIMM Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. PIN 184 Data ...