MT9VDVF6472Y-335D4 Micron Technology Inc, MT9VDVF6472Y-335D4 Datasheet - Page 21

• Manufacturer Part Number: MT9VDVF6472Y-335D4
• Description: MODULE DDR 512MB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9VDVF6472Y-335D4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Package Type: VLP DIMM
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14:
Table 15:
PDF: 09005aef81cf6969/Source: 09005aef81cf67b0
DVF9C32_64x72_2.fm - Rev. A 8/05 EN
AC Characteristics
Parameter
AC Characteristics
Parameter
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
DDR Device Electrical Characteristics and Recommended AC Operating Conditions (-335,
-262) (Continued)
Notes: 1–5, 8, 10, 12; notes appear on pages 23–26; 0°C ≤ T
DDR Device Electrical Characteristics and Recommended AC Operating Conditions (-26A,
-265, -202)
Notes: 1–5, 8, 10, 12; notes appear on pages 23–26; 0°C ≤ T
DD
CL = 2.5
CL = 2
256MB, 512MB: (x72, SR) 184-Pin DDR VLP RDIMM
21
Symbol
Symbol
t
t
t
t
t
t
t
XSNR
XSRD
t
t
DQSCK
t
REFC
t
CK (2.5)
t
t
t
REFI
VTD
CK (2)
DQSQ
DQSH
t
DIPW
DQSL
DQSS
t
t
t
t
t
MRD
t
t
QHS
t
t
t
DSH
t
t
t
t
RAP
t
t
DSS
t
t
IPW
RAS
t
QH
AC
CH
DH
DS
HP
HZ
IH
IH
RC
CL
IS
IS
LZ
F
S
F
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A
A
Min
200
-0.75
-0.75
-0.75
t
7.5/10
t
Min
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
2.20
75
QHS
HP -
7.5
0.5
0.5
0.2
0.2
≤ +70°C; V
0
≤ +70°C; V
15
20
65
40
1
1
-26A/-265
t
CH,
-335
120,000
+0.75
t
+0.75
+0.75
Max
Max
0.55
0.55
1.25
CL
0.75
70.3
0.5
13
7.8
13
DD
DD
= V
= V
Electrical Specifications
t
t
Min
0.45
0.45
0.35
0.35
0.75
2.20
-0.8
-0.8
-0.8
QHS
HP -
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
DD
DD
10
16
20
70
Min
40
200
8
2
75
0
Q = +2.5V ±0.2V
Q = +2.5V ±0.2V
t
CH,
©2004 Micron Technology, Inc. All rights reserved.
-202
-262
120,000
t
Max
+0.8
+0.8
0.55
0.55
+0.8
1.25
Max
CL
0.6
70.3
13
13
7.8
1
Units Notes
Units
t
t
t
t
t
t
t
t
µs
µs
ns
ns
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Notes
40, 46
40, 46
23, 27
23, 27
22, 23
22, 23
31, 49
16, 8
16, 8
21
21
26
26
27
30
12
12
12
12