MT18VDDT12872AG-335F1 Micron Technology Inc, MT18VDDT12872AG-335F1 Datasheet - Page 7

• Manufacturer Part Number: MT18VDDT12872AG-335F1
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT12872AG-335F1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.62A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
MT18VDDT12872 are high-speed CMOS, dynamic
random-access, 256MB, 512MB, and 1GB memory
modules organized in x72 (ECC) configuration. DDR
SDRAM modules use internally configured quad-bank
DDR SDRAM devices.
tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0–A11 select
device row for 256MB, A0–A12 select device row for
512MB and 1GB). The address bits registered coinci-
dent with the READ or WRITE command are used to
select the device bank and the starting device column
location for the burst access.
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
SDRAM modules allows for concurrent operation,
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
The
DDR SDRAM modules use a double data rate archi-
A bidirectional data strobe (DQS) is transmitted
DDR SDRAM modules operate from differential
Read and write accesses to DDR SDRAM modules
DDR SDRAM modules provide for programmable
The pipelined, multibank architecture of DDR
MT18VDDT3272A,
MT18VDDT6472,
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
and
7
thereby providing high effective bandwidth by hiding
row precharge and activation time.
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible.
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, or 512Mb DDR SDRAM compo-
nent data sheets.
Serial Presence-Detect Operation
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
mode of operation of DDR SDRAM devices. This defi-
nition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 4, Mode Register Definition Diagram, on
page 8.
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(256MB) or A7–A12 (512MB and 1GB) specify the oper-
ating mode.
An auto refresh mode is provided, along with a
DDR SDRAM modules incorporate serial presence-
The mode register is used to define the specific
Reprogramming the mode register will not alter the
Mode register bits A0–A2 specify the burst length,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
The mode register is programmed via the
©2004 Micron Technology, Inc.
For more
2
C bus