MT18VDDT12872AG-335F1 Micron Technology Inc, MT18VDDT12872AG-335F1 Datasheet - Page 15

• Manufacturer Part Number: MT18VDDT12872AG-335F1
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT12872AG-335F1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.62A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 14: I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
PARAMETER/CONDITION
NOTE:
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4;
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs
(BL = 4) with auto precharge,
Address and control inputs change only during Active READ, or
WRITE commands
RC =
CK =
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
t
t
t
RC (MIN);
CK MIN; CKE = HIGH; Address and other control inputs
CK =
t
RC =
t
t
CK =
CK (MIN); I
t
DD
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
Specifications and Conditions – 1GB
t
CK (MIN); DQ, DM and DQS inputs
OUT
t
RC =
t
CK =
t
t
CK =
CK =
= 0mA
t
t
RC =
RAS (MAX);
t
0.2V
t
CK (MIN); CKE = (LOW)
IN
CK (MIN); CKE = LOW
t
CK (MIN); I
= V
t
RC (MIN);
REF
for DQ, DQS, and DM
t
CK =
OUT
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
t
CK =
t
t
Standard
= 0mA; Address
REFC =
REFC = 7.8125µs
t
CK (MIN); DQ,
t
CK (MIN);
t
RFC (MIN)
T
A
15
+70°C; V
I
I
I
I
I
I
I
SYM
DD4W
I
I
I
DD3N
DD5A
I
I
DD
DD2P
DD2F
DD3P
DD4R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD0
DD1
DD6
DD7
184-PIN DDR SDRAM UDIMM
5
= V
a
a
b
a
b
b
b
b
a
b
b
a
DD
Q = +2.6V ±0.1V
MAX
1,440
1,710
1,080
1,755
1,800
6,210
4,095
-40B
990
810
198
90
90
DD
2
P
(CKE LOW) mode.
UNITS
©2004 Micron Technology, Inc.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
21, 41
21, 41
21, 41
24, 43
20, 42
43
44
43
21
43
9