MT18VDVF12872DG-40BD4 Micron Technology Inc, MT18VDVF12872DG-40BD4 Datasheet - Page 7

• Manufacturer Part Number: MT18VDVF12872DG-40BD4
• Description: MODULE DDR 1GB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872DG-40BD4

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
27, 29, 32, 37, 41, 43, 48,
115, 118, 122, 125, 130,
5, 14, 25, 36, 47, 56, 67,
44, 45, 49, 51, 134, 135,
97, 107, 119, 129, 140,
149, 159, 169, 177
Pin Numbers
63, 65, 154
137, 138
157, 158
142, 144
21,111
52, 59
78, 86
141
10
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
WE#, CAS#, RAS#
DQS0–DQS8
CKE0, CKE1
DM0–DM8
CK0, CK0#
BA0, BA1
CB0–CB7
Symbol
S0#, S1#
A0–A12
RESET#
Output
Output
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Type
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Asynchronously forces all registered ouputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure CKE
is LOW and DQs are High-Z.
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM state does not affect READ
command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Check Bits.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
DD
is applied.