MT18VDVF12872DG-40BD4 Micron Technology Inc, MT18VDVF12872DG-40BD4 Datasheet
MT18VDVF12872DG-40BD4
Specifications of MT18VDVF12872DG-40BD4
Related parts for MT18VDVF12872DG-40BD4
MT18VDVF12872DG-40BD4 Summary of contents
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... Dual rank PDF: 09005aef81c73825/Source: 09005aef81c73837 DVF18C64_128x72D_1.fm - Rev. A 8/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM www.micron.com/products/modules Figure 1: 184-Pin VLP DIMM (MO-206) Very Low Profile Height 0.72in (18.29mm) Options • Package ...
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... MT18VDVF12872DY-335__ MT18VDVF12872DG-262__ MT18VDVF12872DY-262__ MT18VDVF12872DG-26A__ MT18VDVF12872DY-26A__ MT18VDVF12872DG-265__ MT18VDVF12872DY-265__ MT18VDVF12872DG-202__ MT18VDVF12872DY-202__ Note: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDVF6472DY-265B1. PDF: 09005aef81c73825/Source: 09005aef81c73837 DVF18C64_128x72D_1.fm - Rev. A 8/05 EN 512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM 8K (A0– ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 184-Pin VLP DIMM (MO-206 ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Assignments and Descriptions Table 3: Pin Assignment 184-pin DIMM Front Pin Symbol Pin Symbol Pin DQ17 47 REF 2 DQ0 25 DQS2 DQ1 ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol 10 RESET# 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21,111 CKE0, CKE1 ...
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... Supply Ground. SS Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 8 Pin Assignments and Descriptions Description Micron Technology, Inc ...
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... Unless otherwise noted, resistor values are 22Ω. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. Standard modules use the following DDR SDRAM devices: MT46V32M8FG (512MB) and MT46V64M8FG (1GB). Lead-free modules use the following DDR SDRAM devices: MT46V32M8BG (512MB) and MT46V64M8BG (1GB). ...
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... Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
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SDRAM organizations and timing parameters. The remaining 128 bytes of stor- age are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I bus ...
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Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ com- mand and the availability of the first bit of output data. The latency can be set 2.5 clocks, as ...
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Table 5: Burst Definition Table Burst Length Notes: 1. For a burst length of two, A1–Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four-data-element block; ...
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Figure 5: CAS Latency Diagram CK# COMMAND DQS DQ CK# COMMAND DQS DQ Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero, and bits A0–A6 set to ...
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DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power- up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. When the device exits ...
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Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen- eral reference of available commands. For a more detailed description of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Electrical Specifications Table 11: I Specifications and Conditions – 512MB DD DDR SDRAM Components Only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 22–26; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 12: I Specifications and Conditions – 1GB DD DDR SDRAM Components Only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 22–26; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 13: Capacitance (512MB only) Note: 11; notes appear on pages 22–26 Parameter Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 14: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM ...
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Table 14: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM components only Notes: 1–5, 12–15, 29, 48; notes appear on pages 22–26; 0°C ≤ Characteristics Parameter ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output ...
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HZ and tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion ...
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Figure 7: Derating Data Valid Window ( 3.8 3.750 3.700 3.6 3.4 3.2 NA -335 -262/-26A/-265 @ 10ns 3.0 -262/-26A/-265 @ 7.5ns 2.8 2.6 2.500 2.463 2.4 2.2 2.0 1.8 50/50 49.5/50.5 32. Any ...
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V IH not be greater than 1/3 of the cycle rate. V width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36 37. HZ (MAX) will prevail over ...
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remain stable. Although I 45. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 46. Leakage number reflects ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic LOW. 4. Provide stable clock signals. 5. Wait at ...
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Figure 10: Initialization Flow Diagram Step PDF: 09005aef81c73825/Source: 09005aef81c73837 DVF18C64_128x72D_2.fm - Rev. A 8/05 EN 512MB, 1GB: (x72, DR) ...
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Register and PLL Specifications Table 15: Register Timing Requirements and Switching Characteristics Note 1 Register Symbol Paramerter f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL t Pulse Duration w SSTL (bit pattern ...
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Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 Parameter Symbol Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter t Half-Period Jitter Input Clock Slew ...
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... The component case temperature measurements shown above were obtained experimen- tally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case tem- peratures charted represent worst-case component locations on modules installed in the internal slots of the system ...
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Serial Presence-Detect SPD Clock And Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 12, "Data Valid- ity," on page ...
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Figure 13: Definition of Start and Stop SCL SDA Figure 14: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef81c73825/Source: 09005aef81c73837 DVF18C64_128x72D_2.fm - Rev. A 8/05 EN 512MB, 1GB: (x72, DR) 184-Pin ...
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Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first Select Code Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes Mode RW Bit Current Address Read Random Address Read ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA OUT Input Leakage Current: ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 37 Byte Description 0 Number of SPD Bytes used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type ...
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... Release 1.0 -335 -262 -26A -265 MICRON (Continued) 01–12 1 set to 7ns (0x70) for optimum BIOS compatibility. Actual device specifi- t RAS used for -26A/-265 modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 37 Serial Presence-Detect MT18VDVF6472D MT18VDVF12872D ...
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Module Dimensions All dimensions in inches (millimeters) Figure 16: 184-Pin VLP RDIMM Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. U12 U13 U14 ...