MT18VDVF12872DG-40BD4 Micron Technology Inc, MT18VDVF12872DG-40BD4 Datasheet - Page 22

• Manufacturer Part Number: MT18VDVF12872DG-40BD4
• Description: MODULE DDR 1GB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872DG-40BD4

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
10. I
11. This parameter is sampled. V
12. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate is less
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
14. Inputs are not recognized as valid until V
15. The output timing reference level, measured at the timing reference point indicated in
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
Output
(V
OUT
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
but input timing is still referenced to V
parameter specifications are guaranteed for the specified AC input levels under normal
use conditions. The minimum slew rate for the input signals used to test the device is
1V/ns in the range between V
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
the DC level of the same. Peak-to-peak noise (non-common mode) on V
exceed ±2 percent of the DC value. Thus, from V
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest V
resistors, is expected to be set equal to V
of V
with minimum cycle time at CL = 2 for -262, and -26A, CL = 2.5 for-335 and -265 with
the outputs open.
the defined cycle rate.
MHz, T
with I/O pins, reflecting the fact that they are matched in loading.
than 0.5 V/ns, timing must be derated:
reduction in slew rate from 500 mV/ns, while
V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
before V
Note 3, is V
DD
DD
REF
REF
TT
)
REF
specifications are tested after the device is properly initialized, and is averaged at
is not applied directly to the device. V
is dependent on output loading and cycle rates. Specified values are obtained
.
is expected to equal V
V
.
TT
A
REF
50
30pF
= 25°C, V
REF
Reference
Point
Ω
TT
stabilizes, CKE ≤ 0.3 x V
.
by-pass capacitor.
DD
OUT
tests may use a V
DD
(
DC
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
, and electrical AC and DC characteristics may be conducted
) = V
22
DDQ
SS
IL
.
DD
DDQ
(
AC
/2 of the transmitting device and to track variations in
= +2.5V ±0.2V, V
) and V
/2, V
IL
DDQ
-to-V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
REF
t
IS has an additional 50ps per each 100 mV/ns
is recognized as LOW.
IH
REF
IH
REF
(
TT
AC
(peak to peak) = 0.2V. DM input is grouped
(or to the crossing point for CK/CK#), and
swing of up to 1.5V in the test environment,
and must track variations in the DC level
is a system supply for signal termination
).
t
stabilizes. Exception: during the period
IH is unaffected. If slew rate exceeds 4.5
DDQ
DDQ
/2, V
= +2.5V ±0.2V, V
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
REF
is allowed ±25mV for DC
REF
= V
REF
SS
may not
Notes
, f = 100