MT9VDDF3272G-40BG3 Micron Technology Inc, MT9VDDF3272G-40BG3 Datasheet - Page 20

• Manufacturer Part Number: MT9VDDF3272G-40BG3
• Description: MODULE DDR SDRAM 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF3272G-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1130

pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -40B, I
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
160
140
120
100
80
60
40
20
Figure 8: Pull-Down Characteristics
0
0.0
equal to or less than V
may be 1.35V maximum during power up, even if
V
series resistance is used between the V
and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
SDRAM device at 100 MHz.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
DD
/V
DDQ
0.5
DD
are 0V, provided a minimum of 42
3N is specified to be 35mA per DDR
1.0
V
V
DD
OUT
OUT
DDQ
(V)
(V)
+ 0.3V. Alternatively, V
, V
1.5
TT
, and V
2.0
REF
Minimum
TT
must be
supply
TT
2.5
of
256MB, 512MB (x72, ECC, SR) PC3200
20
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. This is the DC voltage supplied at the DRAM and
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic high or logic low.
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±100mV.
Figure 9: Pull-Up Characteristics
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
2N specifies the DQ, DQS, and DM to be
2F is “worst case.”
0.5
DD
DD
2F, I
2F except I
DD
1.0
V
DD
2N, and I
Q - V
©2004 Micron Technology, Inc. All rights reserved.
OUT
(V)
1.5
DD
DD
2Q specifies the
2Q are similar,
2.0
DD
2Q is
2.5