MT9VDDF3272G-40BG3 Micron Technology Inc, MT9VDDF3272G-40BG3 Datasheet - Page 12

• Manufacturer Part Number: MT9VDDF3272G-40BG3
• Description: MODULE DDR SDRAM 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF3272G-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1130

Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (256MB) or A0–A9, A11 (512MB )provide column address; A10 HIGH
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
Table 8, Commands Truth Table, and Table 9, DM
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
256MB, 512MB (x72, ECC, SR) PC3200
12
CS#
H
L
L
L
L
L
L
L
L
of commands and operations, refer to the 256Mb or
512Mb DDR SDRAM component data sheets.
RAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
X
H
H
H
H
L
L
L
L
CAS# WE#
X
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
©2004 Micron Technology, Inc. All rights reserved.
Code
X
X
X
X
DM
H
L
NOTES
6, 7
1
1
2
3
3
4
5
8
Valid
DQS
X