MT9VDDF3272G-40BG3 Micron Technology Inc, MT9VDDF3272G-40BG3 Datasheet - Page 19

• Manufacturer Part Number: MT9VDDF3272G-40BG3
• Description: MODULE DDR SDRAM 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF3272G-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1130

pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
by the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncertain.
For -40B, slew rates must be 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+300mV (2.9V max), whichever is less. Any nega-
tive glitch must be less than 1/3 of the clock cycle
and not exceed -200mV (2.3V min), whichever is
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
t
QH =
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
must not vary more than 4 percent if CKE is
t
IH
IH
HP -
(AC).
(DC).
t
QHS). The data valid window derates
t
HP (
t
t
t
CK/2),
CL minimum and
RAS(MIN) can be satis-
t
RFC [MIN]) else
t
DQSQ, and
t
DS and
IL
IL
(DC)
(AC)
t
t
QH
CH
256MB, 512MB (x72, ECC, SR) PC3200
19
33. Normal Output Drive Curves:
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
more positive. However, the DC average cannot be
below 2.4V minimum.
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
width 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. V
= -1.5V for a pulse width 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current from
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
DD
RPST), or begins driving (
184-PIN DDR SDRAM RDIMM
from minimum to maximum process, tempera-
ture and voltage will lie within the outer bound-
ing lines of the V-I curve of Figure 8, Pull-Down
Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 9, Pull-Up Charac-
teristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
overshoot: V
and V
t
DQSCK (MIN) +
DD
DDQ
level and the referenced test load. In
must track each other.
IH
(MAX) = V
t
RPRE (MAX) condition.
t
RPRE begin point are not
©2004 Micron Technology, Inc. All rights reserved.
IL
t
t
LZ (MIN) will prevail
RPRE).
DDQ
undershoot: V
t
DQSCK (MAX) +
+ 1.5V for a pulse
IL
(MIN)