MT9VDDF3272G-40BG3 Micron Technology Inc, MT9VDDF3272G-40BG3 Datasheet - Page 11

• Manufacturer Part Number: MT9VDDF3272G-40BG3
• Description: MODULE DDR SDRAM 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF3272G-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1130

TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power.
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
All other combinations of values for A7–A12 are
The extended mode register controls functions
The extended mode register must be loaded when
The
256MB, 512MB (x72, ECC, SR) PC3200
11
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. When the device exits self refresh mode, the DLL
is enabled automatically. Any time the DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ command can be issued.
NOTE:
E12
1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the
2. QFC# is not supported.
0
–
The DLL must be enabled for normal operation.
Extended Mode Register (vs. the base Mode Register).
Figure 7: Extended Mode Register
E11
0 1
14
BA1 BA0
0
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
1 1
E10
13
0
–
12
E9
A12
0
–
11
E8
A11
0
–
Definition Diagram
E7
10
0
–
A10
E6 E5
0
–
9
Operating Mode
A9
0
–
8
A8
E4
0
–
7
A7 A6 A5 A4 A3
E3
0
–
6
E2 2
0
–
5
©2004 Micron Technology, Inc. All rights reserved.
4
E1,
Valid
–
3
E0
2
A2 A1 A0
DS
Operating Mode
Reserved
Reserved
1
E1
0
DLL
0
E0
0
1
Drive Strength
Extended Mode
Register (Ex)
Address Bus
Normal
Disable
Enable
DLL