MT9VDDT3272AY-40BK1 Micron Technology Inc, MT9VDDT3272AY-40BK1 Datasheet - Page 9

• Manufacturer Part Number: MT9VDDT3272AY-40BK1
• Description: MODULE DDR 256MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT3272AY-40BK1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Idd Specifications
Table 9:
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
and control inputs changing once every 2 clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ, DM, and DQS
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
control inputs change only during active READ or WRITE commands
CK =
CK =
RC =
CK =
CK =
t
t
t
t
t
CK (MIN); Iout = 0mA; Address and control inputs changing once per clock
RAS (MAX);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address
CK (MIN); Iout = 0mA
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
t
CK =
CK =
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
Idd Specifications and Conditions – 256MB (Die Revision K)
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
RC =
t
RC (MIN);
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
t
CK =
t
RC =
t
CK (MIN); Address and
t
RC (MIN);
t
CK =
t
t
9
RFC =
RFC = 7.8125µs
t
t
RC =
CK (MIN);
t
RFC (MIN)
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RC (MIN);
Symbol
Idd4W
Idd3N
Idd5A
Idd2P
Idd3P
Idd4R
Idd2F
Idd0
Idd1
Idd5
Idd6
Idd7
Electrical Specifications
©2003 Micron Technology, Inc. All rights reserved.
-40B
1080
1620
1620
1440
2610
900
450
315
540
36
54
36
1035
1440
1440
1440
2430
-335
810
450
270
495
36
54
36
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA