MT9VDDT3272AY-40BK1 Micron Technology Inc, MT9VDDT3272AY-40BK1 Datasheet - Page 4

• Manufacturer Part Number: MT9VDDT3272AY-40BK1
• Description: MODULE DDR 256MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT3272AY-40BK1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C32_64x72A.fm - Rev. F 10/08 EN
RAS#, CAS#,
DQS0–DQS8
DQ0–DQ63
CK0, CK0#,
CK1, CK1#,
DM0–DM8
CK2, CK2#
Vdd/Vddq
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
A0–A12
Vddspd
CKE0
WE#
SDA
Vref
S0#
SCL
Vss
NC
Pin Descriptions
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQ and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal
clock, input buffers, and output drivers.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of
DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs: These pins are used to configure the SPD EEPROM address
range on the I
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer
to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V)
SPD EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (Vdd/2).
Ground.
No connect: These pins are not connected on the module.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
2
C bus.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2003 Micron Technology, Inc. All rights reserved.