IDT89TTM553BL IDT, Integrated Device Technology Inc, IDT89TTM553BL Datasheet - Page 9

• Manufacturer Part Number: IDT89TTM553BL
• Description: IC TRAFFIC MANAGER 960-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89TTM553BL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89TTM553BL

IDT 89TTM553
IDDQ
RESERVE_1
SCAN_EN
RESERVE_0
TCK
TDI
TDO
TMS
TRST_N
PLL_2X_BPCLK
PLL_BP_MODE
PLL_MON
PLL_CFG_OVR
PLL_RST
PLL_VDDA
PLL_VSSA
PLL_SYS_REFCLK
RESET_N
VDD18
VDD15
Signal Name
Signal Name
3.3V,
internal pulldown
3.3V LVTTL,
4 mA drive
3.3V
3.3V,
internal pullup
3.3V
3.3V,
internal pullup
3.3V LVTTL,
12 mA drive
3.3V,
internal pullup
3.3V,
internal pullup
3.3V,
internal pulldown
3.3V,
internal pulldown
3.3V LVTTL,
12mA drive
3.3V,
internal pulldown
3.3V
1.8V
—
3.3V
3.3V,
internal pullup
—
—
I/O Type
I/O Type
Table 11 PLL I/O (Part 1 of 2)
Dir.
Dir.
—
—
—
—
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 10 Test I/O
9 of 30
100 MHz
Freq.
Freq.
Async
Async
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
—
—
—
—
—
—
—
—
—
IDDQ input (active high).
For IDT use only. Do not connect.
For IDT use only. Do not connect.
Scan enable (active high)
For IDT use only. Attach to a 4.7K resistor to 0V
Tristate enable (active low)
For IDT use only.
Attach to a 4.7K resistor to 3.3V
JTAG (IEEE 1149.1) clock input.
JTAG (IEEE 1149.1) test data input.
JTAG (IEEE 1149.1) test data output.
JTAG (IEEE 1149.1) test mode select
JTAG (IEEE 1149.1) test reset input.
Bypass Clock Input
For IDT use only. Do not connect.
Bypass Clock Input
For IDT use only. Do not connect.
PLL Monitor
For IDT use only. Do not connect.
PLL Configuration Override
PLL reset. A special initialization sequence is required.
PLL Analog VDD
PLL Analog VSS
Chip core PLL reference clock.
Chip reset input (active low).
1.8V core power
1.5V I/O power for HSTL-2 I/Os: Isolated output buffer supply
set nominally to 1.5V
Remarks
Remarks
March 3, 2005