IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES48T12ZABR
• Description: IC PCI SW 48LANE 12PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES48T12ZABR

SMBus Interface
every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register
values of the PES48T12 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used
by an external Hot-Plug I/O expander.
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
3(a), the master and slave SMBuses are tied together and the PES48T12 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES48T12 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES48T12 may be configured to operate in a split configuration as shown in Figure 3(b).
The PES48T12 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
IDT 89PES48T12 Data Sheet
The PES48T12 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES48T12, allowing
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
PES48T12
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
...
Devices
SMBus
Other
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
3 of 46
0
1
1
(b) Split Configuration and Management Buses
PES48T12
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
1
0
1
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
December 21, 2006