IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 15

• Manufacturer Part Number: IDT89HPES48T12ZABR
• Description: IC PCI SW 48LANE 12PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES48T12ZABR

System Clock Parameters
AC Timing Characteristics
IDT 89PES48T12 Data Sheet
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
PEREFCLK
Refclk
Refclk
T
V
T
1.
2.
3.
4.
PCIe Transmit
T
UI
T
T
T
MAX-JITTER
L
L
T
T
IDLE
T
T
T
T
PCIe Receive
L
L
R
jitter
SW
TLAT-10
TLAT-20
RLAT-10
RLAT-20
Parameter
TX-RISE
TX-MAX-JITTER
TX-EYE
TX-EYE-MEDIAN-to-
TX-SKEW
TX-IDLE-SET-TO-
EIExit
BTEn
RxDetectEn
RxDetect
, T
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
AC coupling required.
Parameter
F
FREQ
DC
2
, T
TX-FALL
Input reference clock frequency range
Duty cycle of input clock
Rise/Fall time of input clocks
Differential input voltage swing
Input clock jitter (cycle-to-cycle)
Rise / Fall time of TxP, TxN outputs
Unit Interval
Transmitter Total Jitter (peak-to-peak)
Minimum Tx Eye Width (1 - T
Maximum time between the jitter median and maximum
deviation from the median
Transmitter data latency (for n=10)
Transmitter data latency (for n=20)
Transmitter data skew between any 2 lanes
Maximum time to transition to a valid electrical idle after
sending an Electrical Idle ordered set
Time to exit Electrical Idle (L0s) state into L0
Time from asserting Beacon TxEn to beacon being trans-
mitted on the lane
Pulse width of RxDetectEn input
RxDetectEn falling edge to RxDetect delay
Recover data latency for n=10
Recover data latency for n=20
Description
Description
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
TX-MAX-JITTER
4
Table 9 Input Clock Requirements
)
15 of 46
399.88
Min
Min
0.75
100
9.8
0.6
40
80
28
49
9
9
Typical
Typical
400
500
10
12
30
50
4
1
0.2*RCUI
400.12
Max
0.25
Max
1300
110
0.15
10.2
125
125
11
11
16
80
29
60
1.6
60
6
2
1
2
1
December 21, 2006
Units
Unit
RCUI
bits
bits
bits
bits
MHz
ps
ps
UI
UI
UI
ps
ns
ns
ns
ns
ns
ps
%
V
3