IDT72T55268L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55268L6-7BBI Datasheet - Page 4

• Manufacturer Part Number: IDT72T55268L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L6-7BBI

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L6-7BBI

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FEATURES (CONTINUED)
FUNCTIONAL BLOCK DIAGRAMS (CONTINUED)
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
- Fully independent status flags for every Queue
- Composite Full/Input Ready Flag monitors currently selected Queue
- Dedicated partial reset for every Queue
Up to 200MHz operating frequency or 8Gbps throughput in SDR mode
Up to 100MHz operating frequency or 8Gbps throughput in DDR mode
User selectable Single Data Rate (SDR) or Double Data Rate
(DDR) modes on both the write port(s) and read port(s)
All I/O are LVTTL/ HSTL/ eHSTL user selectable
3.3V tolerant inputs in LVTTL mode
ERCLK and EREN Echo outputs on all read ports
Write Chip Select WCS input for each write port
Read Chip Select RCS input for each read port
User Selectable IDT Standard mode (using EF and FF flags) or
FWFT mode (using IR and OR flags)
Data In
CFF/ CIR
FF0/ IR0
FF1/ IR1
FF2/ IR2
FF3/ IR3
WCLK0
WEN0
WCS0
IS[1:0]
x10,x20,x40
D[39:0]
PAF0
PAF1
PAF2
PAF3
2
Demux Mode
32,768 x 40
32,768 x 40
32,768 x 40
32,768 x 40
16,384 x40
16,384 x40
16,384 x40
16,384 x40
8,192 x 40
8,192 x 40
8,192 x 40
8,192 x 40
4
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Composite Full/ Input Ready Flag in Demux and Broadcast
mode
Composite Empty/ Output Ready flag in Mux mode
Independent Programmable Almost Empty and Almost Full flags
per Queue
Dedicated Serial Port for flag programming
Dedicated Partial Reset for each individual Queue
Power Down pin minimizes power consumption
2.5V Supply Voltage
Available in a 324-pin Plastic Ball Grid Array (PBGA)
19mm x 19mm, 1mm Pitch
IEEE 1149.1 compliant JTAG port provides boundary scan
function, or flag programming
Low Power, High Performance CMOS technology
Industrial temperature range (-40° ° ° ° ° C to +85° ° ° ° ° C)
Queue 0
Queue 1
Queue 2
Queue 3
6157 drw02
10
10
10
10
COMMERCIAL AND INDUSTRIAL
EF0/ OR0
PAE0
EF1/ OR1
PAE1
EF2/ OR2
PAE2
EF3/ OR3
PAE3
RCLK0
REN0
RCS0
OE0
Q[9:0]
RCLK1
REN1
RCS1
OE1
Q[19:10]
RCLK2
REN2
RCS2
OE2
Q[29:20]
RCLK3
REN3
RCS3
OE3
Q[39:30]
TEMPERATURE RANGES
FEBRUARY 01, 2009
Data Out
Data Out
Data Out
Data Out
Queue 3
Queue 0
Queue 1
Queue 2