IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 32

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

ing RCLK will enable the output bus. When the read chip select goes HIGH,
the next rising edge of RCLK will send the output bus into high-impedance and
prevent that RCLK from initiating a read, regardless of the state of REN. During
a master or partial Reset the read chip select input has no effect on the output
bus, output enable (OE[3:0]) is the only input that provides high-impedance
control of the output bus. If output enable is LOW, the data outputs will be active
regardless of read chip select until the first rising edge of RCLK after a reset is
complete. Afterwards if read chip select is HIGH the data outputs will go to high-
impedance. The four read chip selects are completely independent of one
another.
when the first word is written to any/all empty Queues, the empty flag(s) will still
go from LOW to HIGH based on a rising edge of the RCLK(s), regardless of
the state of the read chip select inputs. Also, when operating the Queue in FWFT
mode the first word written to any/all empty Queues will still be clocked through
to the output bus on the third rising edge of RCLK(s), regardless of the state of
read chip select inputs, assuming that the t
the user should pay extra attention to the read chip selects when a data word
is written to any/all empty Queues in FWFT mode. If the read chip select inputs
are HIGH when an empty Queue is written into, the first word will fall through
to the output register but will not be available on the outputs because they are
in high-impedance. The user must enable the read chip selects on the next rising
edge of RCLK to access this first word.
should be tied to V
READ DOUBLE DATA RATE (RDDR)
set to double data rate mode, sampled during master reset. In this mode, all read
operations are based on the rising and falling edge of the read clocks, provided
that read enables and read chip selects are LOW. In double data rate mode,
the read enable signals are sampled with respect to the rising edge of read clock
only, and a word will be read from both the rising and falling edge of read clock
regardless of whether or not read enable and read chip select are active on
the falling edge of read clock.
data rate mode. In this mode, all read operations are based on only the rising
edge of the read clocks, provided that read enables and read chip selects are
LOW during the rising edge of read clock. This pin should be tied HIGH or LOW
and cannot toggle before and after master reset.
OUTPUT ENABLE (OE0/1/2/3)
this device, each corresponding to the individual Queues in memory. When the
output enable inputs are LOW, the output bus of each individual Queue become
active and drives the data currently in the output register. When the output enable
inputs (OE[3:0]) are HIGH, the output bus of each individual Queue goes into
high-impedance. During master or partial Reset the output enable is the only
input that can place the output data bus into high-impedance. During reset the
read chip select input has no effect on the output data bus. The four output enable
inputs are completely independent of one another.
should be tied to GND.
I/O SELECT (IOSEL)
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The read chip select inputs do not affect the updating of the flags. For example,
In Mux mode, only the RCS0 input is available. All other read chip select inputs
When the read double data rate (RDDR) pin tied HIGH, the read port will be
When RDDR is tied LOW at master reset, the read port will be set to single
There are a possible total of four asynchronous output enables available in
In Mux mode, only the OE0 input is available. All other output enable inputs
The inputs and outputs of this device can be configured for either LVTTL or
CC
.
SKEW
parameter is met. For this reason
32
operating voltage levels. To select between HSTL or eHSTL VREF must be
driven to 0.75V or 0.9V respectively.
HSTL signals will be configured for LVTTL operating voltage levels. In this
configuration VREF should be set to the static core voltage of 2.5V.
reset. Please refer to table 5 for a list of applicable LVTTL/HSTL/eHSTL signals.
POWER DOWN (PD)
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN and REN signals must be disabled for a minimum of four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down
time. During power down, the following conditions for the inputs/outputs signals
are:
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a minimum of 1µs waiting period before
read and write operations can resume. The device will continue from where it
had stopped, no form of reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to V
for the associated timing diagram.
SERIAL CLOCK (SCLK)
offset registers. Data from the serial input signal (FWFT/SI) can be loaded into
the offset registers on the rising edge of SCLK provided that the serial write
enable (SWEN) signal is LOW. Data can be read from the offset registers via
the serial data output (SDO) signal on the rising edge of SCLK provided that
SREN is LOW. The serial clock can operate at a maximum frequency of 10MHz.
The read operation is non-destructive. However, the write operation will
change the flag offsets on each SCLK rising edge as data shifts into the registers.
SERIAL WRITE ENABLE (SWEN)
programmable offset registers. It is used in conjunction with the serial input
If the IOSEL pin is LOW during master reset, then all applicable LVTTL or
This pin should be tied HIGH or LOW and cannot toggle before or after master
This device has a power down feature intended for reducing power
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All internal counters, registers, and flags will remain unchanged and maintain
The serial clock is used to load data and read data from in the programmable
The serial write enable input is an enable used for serial programming of the
All data in Queue(s) are retained.
All data inputs become inactive.
All write and read pointers maintain their last value before power down.
All enables, chip selects, and clock input pins become inactive.
All data outputs become inactive and enter high-impedance state.
All flag outputs will maintain their current states before power down.
All programmable flag offsets maintain their values.
All echo clocks and enables will become inactive and enter
high-impedance state.
The serial programming and JTAG port will become inactive and enter
high-impedance state.
All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
CC
or GND. See Figure 39, Power Down Operation
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009