IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 30

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT BUS (D[39:0])
mode. D[39:0] are data inputs for the 40-bit wide data bus, D[19:0] are data
inputs for 20-bit wide data bus, and D[9:0] are data inputs for the 10-bit wide
data bus. In Mux mode the input bus will be 10 bits wide for each of the four
internal Queues. D[9:0] are dedicated to Queue 0, D[19:10] are dedicated to
Queue 1, D[29:20] are dedicated to Queue 2, and D[39:30] are dedicated to
Queue 3. Data can be written into each of the four Queues on every WCLK
cycle. There is a two cycle input pipeline and a two cycle output pipeline. It will
take two cycles or three rising edges of the WCLK to move data from the write
port to the queue and two cycles or those rising edges of RCLK to move data
from the queue to the data outlines.
MASTER RESET (MRS)
A master reset is accomplished whenever the MRS input is taken to a LOW state.
This operation sets the internal read and write pointers of all Queues to the first
location in memory. The programmable almost empty flag will go LOW and the
almost full flags will go HIGH.
selected. This mode utilizes the empty and full status flags from the EF/OR and
FF/IR dual-purpose pin. During master reset, all empty flags will be set to LOW
and all full flags will be set to HIGH.
Through mode is selected. This mode utilizes the input read and output ready
status flags from the EF/OR and FF/IR dual-purpose pin. During master reset,
all input ready flags will be set to LOW and all output ready flags will be set to
HIGH.
OS[1:0], WDDR, RDDR, IOSEL, PFM, FSEL[1:0] and FWFT/SI needs to be
defined before the master reset cycle. During a master reset the output register
is initialized to all zeros. If the output enable(s) are LOW during master reset,
then the output bus will be LOW. If the output enable(s) are HIGH during master
reset, then the output bus will be in High-impedance. RCS has no affect on the
data outputs during master reset. If the output width OW[1:0] is configured to
x10 or x20, then the unused outputs will be in high-impedance. A master reset
is required after power up before a write operation to any Queue can take place.
Master reset is an asynchronous signal and thus the read and write clocks can
be free-running or idle during master reset. See Figure 10, Master Reset
Timing, for the associated timing diagram.
PARTIAL RESET (PRS0/1/2/3)
pointers of each individual Queue inside the device without changing the
Queue’s configuration. There are four dedicated partial reset signals that each
correspond to an individual Queue. There are restrictions as to when partial
reset can be performed that apply to each operating modes.
during Queue selection on the read port. For instance, if OS[1:0] is switching
from 00 to 01 then PRS0 and PRS1 may not be enabled from the first rising RCLK
edge with OS[1:0]=01 until three more rising RCLK edges have been received.
In other words, partial reset may not be performed for a minimum of three RCLK
cycles from the time a new Queue is selected. Also, if Queue0 or Queue1 are
partially reset before the switch, the appropriate PRS signal must return HIGH
at least t
Any Queues not involved in the selection can be partially reset.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The data input bus can be 40, 20, or 10 bits wide in Demux and Broadcast
There is a single master reset available for all internal Queues in this device.
If FWFT/SI signal is LOW during master reset then IDT Standard mode is
If FWFT/SI signal is HIGH during master reset, then the First Word Fall
All device configuration pins such as MD[1:0], OW[1:0], IW[1:0], IS[1:0],
A partial reset is a means by which the user can reset both the read and write
In Mux mode, partial reset may not be performed on the two Queues involved
RSR
(reset recovery time) before the first RCLK edge with OS[1:0]=01.
30
involved during Queue selection on the write port. For instance, if IS[1:0] is
switching from 11 to 10 then PRS3 and PRS2 may not be enabled from the first
rising WCLK edge with OS[1:0]=01 until three more rising WCLK edges have
been received. In other words, partial reset may not be performed for a minimum
of three WCLK cycles from the time a new Queue is selected. Also, if Queue0
or Queue1 are partially reset before the switch, the appropriate PRS signal must
be HIGH at least t
IS[1:0]=10. Any Queues not involved in the selection can be partially reset.
operations. The write enable and write chip select must be HIGH with respect
to the rising edge of WCLK0 for a minimum of t
performed. If the device is operating in DDR mode, partial reset of any Queue
must be initiated after the falling edge of WCLK0 to ensure data from the falling
edge are written into all four Queues in memory. This maintains the data integrity
of all four Queues in the device.
diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
mode will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the Queues memory. It also uses the
Full Flag function (FF) to indicate whether or not the Queues memory has any
free space for writing. In IDT Standard mode, every word read from the
Queues, including the first, must be requested using the Read Enable (REN),
Read Chip Select (RCS) and RCLK.
will be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the Queues have any free space for writing. In the
FWFT mode, the first word written to an empty Queue goes directly to Qn after
three RCLK rising edges, provided that the first RCLK meets t
eters. There will be a one RCLK cycle delay if t
do not need to be enabled. Subsequent words must be accessed using the
REN, RCS, and RCLK. RCS must be LOW or the outputs will be in a High-
state.
minimum of the reset recovery time (t
FWFT/SI acts as a serial input for loading PAE and PAF offsets into the
programmable offset registers. The serial input is used in conjunction with
SCLK, SWEN, SREN, and SDO to access the offset registers. Serial program-
ming using the FWFT/SI pin functions the same way in both IDT Standard and
FWFT modes.
WRITE CLOCK (WCLK0/1/2/3)
depending on the mode selected, each corresponding to the individual Queues
in memory. A write cycle is initiated on the rising and/or falling edge of the WCLK
input. If the write double data rate (WDDR) mode pin is tied HIGH during master
reset, data will be written on both the rising and falling edge of WCLK0/1/2/3,
provided that WEN0/1/2/3 and WCS0/1/2/3 are enabled. If WDDR is tied LOW,
data will be written only on the rising edge of WCLK0/1/2/3 provided that WEN0/
1/2/3 and WCS0/1/2/3 are enabled. The four write clocks are completely
independent of one another.
In Demux mode, partial reset may not be performed on the two Queues
In Broadcast mode, partial reset may not be performed during write
See Figures 11, 12, 13, Partial Reset Timing, for the associated timing
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
If FWFT/SI is LOW before the falling edge of master reset, then IDT Standard
If FWFT/SI is HIGH before the falling edge of master reset, then FWFT mode
The state of the FWFT/SI input must be kept at the present state for the
There are a possible total of four write clocks available in this device
RSR
(reset recovery time) before the first WCLK edge with
RSR
COMMERCIAL AND INDUSTRIAL
) after master reset. After this time, the
SKEW
RSS
TEMPERATURE RANGES
before partial reset can be
is not met. REN and RCS
FEBRUARY 01, 2009
SKEW
param-