IDT72T55268L6-7BB IDT, Integrated Device Technology Inc, IDT72T55268L6-7BB Datasheet - Page 10

• Manufacturer Part Number: IDT72T55268L6-7BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L6-7BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L6-7BB

PIN DESCRIPTIONS (CONTINUED)
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
IW[1:0]
(IW1-C12
IW0-C8)
MD[1:0]
(MD1-B5
MD0-B4)
MRS
(A5)
OE0
(A13)
OE1-(A14)
OE2-(A15)
OE3-(A16)
OS[1:0]
(OS1-V11
OS0-T12)
OW[1:0]
(OW1-B8
OW0-C6)
PAE0-(V3)
PAE1-(V5)
PAE2-(V7)
PAE3-(U10)
PAF0-(U4)
PAF1-(T5)
PAF2-(T7)
PAF3-(T11)
PD
(B12)
PFM
(D4)
PRS0-(A6)
PRS1-(A7)
PRS2-(A8)
PRS3-(A12)
Symbol &
Pin No.
Input Width
Mode Pin
Master Reset
Output Enable 0
Output Enable 1/2/3 HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
Output Select
Output Width
Programmable
Almost Empty Flag
0/1/2/3
Programmable
Almost Full Flag
0/1/2/3
Power Down
Programmable Flag
Mode
Partial Reset
0/1/2/3
Name
HSTL-LVTTL This input provides a full device reset. All set-up pins are sampled based on a master reset operation.
HSTL-LVTTL If Mux mode is selected this is the Output Enable for the read port. All data output pins will be placed
HSTL-LVTTL If Mux mode is selected these inputs select one of the four Queues to be read from on the read port.
HSTL-LVTTL If Mux mode is selected, this pin is used during master reset to select the output word width bus
HSTL-LVTTL This is the programmable almost empty flag that can be used to pre-indicate the empty boundary
HSTL-LVTTL This is the programmable almost full flag that can be used to pre-indicate the full boundary of each
HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input
HSTL-LVTTL These are the partial reset inputs for each internal Queue. The read, write, flag pointers, and output
OUTPUT
OUTPUT
I/O TYPE
CMOS
CMOS
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(1)
(1)
(1)
(2)
(2)
00 = Demux; 10 = Mux; 01 = Broadcast Write; 11 = Restricted.
into High Impedance if this pin is HIGH.
level translators for all the data input pins, clocks and non-essential control pins are turned off.
In Demux or Broadcast, these pins are used during master reset to select the input bus size for the
device. The values are: 00 = x10; 01 = x20; 10 = x40. 11 = Restricted. In Mux mode these pins must
be tied to GND.
This mode selection pin used during Master Reset to select the mode of the Queue. The values are:
Read and write pointers will be reset to the first location memory. All flag offsets are cleared and
reset to default values determined by FSEL[1:0].
If Demux or Broadcast mode is selected this is the output enable pin for Queue 0. All data output
pins of Queue 0 will be placed into High Impedance if this pin is HIGH. This input is asynchronous.
If Demux or Broadcast mode is selected these are the output enable pins Queues 1, 2 and 3
respectively. All data outputs on Queue 1, Queue 2 and Queue 3 will be in High-Impedance if the
respective output enable pin is High. These inputs are asynchronous.
The address on the output select pins is setup with respect to the rising edge of RCLK0.
If Demux or Broadcast mode is selected these inputs are not used and should be tied to GND.
size for the device. The values are: 00 = x10; 01 = x20; 10 = x40; 11 = Restricted.
If Demux or Broadcast mode is selected the output word width will be x10. These pins are not used
and must be tied to GND.
of each Queue. The PAE flags can be set to one of four default offsets determined by the state of
FSEL0 and FSEL1 during master reset. The PAE offset values can also be written and read from
serially by either the JTAG port or the serial programming pins (SCLK, FWFT/SI, SDO, SWEN,
SREN). This flag can operate in synchronous or asynchronous mode depending on the state of the
PFM pin during master reset.
Queue. The PAF flags can be set to one of four default offsets determined by the state of FSEL0 and
FSEL1 during master reset. The PAF offset values can also be written and read from serially by
either the JTAG port or the serial programming pins (SCLK, FWFT/SI, SDO, SWEN, SREN). This
flag can operate in synchronous or asynchronous mode depending on the state of the PFM pin
during master reset.
When PD is brought high, power-up sequence timing will have to be followed to before the inputs
will be recognized. It is essential that the user respect these conditions when powering down the
part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks
are free running. PD does not provide any power consumption savings when the inputs are
configured for LVTTL
During master reset, a HIGH on PFM selects synchronous PAE/PAF flag timing, a Low during
master reset selects asynchronous PAE/PAF flag timing. This pin controls all PAE/PAF flag outputs.
registers will all be set to zero when partial reset is activated. During partial reset, the existing mode
(IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all
retained.
10
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009