IDT89HPES24T6G2ZBALG IDT, Integrated Device Technology Inc, IDT89HPES24T6G2ZBALG Datasheet - Page 12

• Manufacturer Part Number: IDT89HPES24T6G2ZBALG
• Description: IC PCI SW 24LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24T6G2ZBALG

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES24T6G2ZBALG

System Clock Parameters
AC Timing Characteristics
IDT 89HPES24T6G2 Data Sheet
Refclk
T
T
V
V
V
V
V
T
T
T
T
V
V
Duty Cycle
Rise/Fall Matching
Z
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15.
C-RISE
C-FALL
STABLE
PERIOD-AVG
PERIOD-ABS
CC-JITTER
C-DC
IH
IL
CROSS
CROSS-DELTA
RB
MAX
MIN
1.
PCIe Transmit
UI
T
T
MAX-JITTER
T
T
T
Parameter
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. Frequency is set at 100 MHz in the 19mm package.
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE
TX- IDLE-MIN
TX-IDLE-SET-TO-IDLE
Parameter
FREQ
, T
TX-FALL
Input reference clock frequency range
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Absolute single-ended crossing point volt-
age
Variation of V
edges
Ring back voltage margin
Time before V
Average clock period accuracy
Absolute period, including spread-spec-
trum and jitter
Cycle to cycle jitter
Absolute maximum input voltage
Absolute minimum input voltage
Duty cycle
Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
Clock source output DC impedance
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maximum
deviation from the median
TX Rise/Fall Time: 20% - 80%
Minimum time in idle
Maximum time to transition to a valid Idle after sending
an Idle ordered set
Description
CROSS
RB
is allowed
over all rising clock
Description
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
Table 9 Input Clock Requirements
Condition
Single-ended
Single-ended
12 of 51
Differential
Differential
Differential
Differential
Differential
Differential
Min
399.88
0.125
0.75
20
1
Gen 1
Typ
400
9.847
Min
+150
+250
-100
-300
1
100
500
-0.3
0.6
0.6
40
40
Max
400.12
0.125
8
1
Typical
Min
199.94
0.75
0.15
20
20
1
Gen 2
Typ
200
1
10.203
Max
+1.15
+550
+140
+100
2800
125
-150
150
60
60
4
4
Max
200.06
1
8
February 2, 2010
1
Units
Unit
MHz
V/ns
V/ns
ps
ns
ppm
UI
UI
UI
UI
mV
mV
mV
mV
mV
ps
ns
ps
%
%
Ω
V
V