IDT72T6480L10BB IDT, Integrated Device Technology Inc, IDT72T6480L10BB Datasheet - Page 26

• Manufacturer Part Number: IDT72T6480L10BB
• Description: IC FLOW-CTRL 48BIT 10NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L10BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L10BB

EMPTY FLAG (EF/OR)
function is selected. When the SFC is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the SFC is not empty. Figure 10, Empty
Boundary – IDT Standard Mode for the relevant timing information.
at the same time that the first word written to an empty SFC appears valid on the
outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the
last word from the SFC to the outputs. OR goes HIGH only with a true read
(RCLK with REN = LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until OR goes LOW
again. See Figure 11, Empty Boundary (FWFT Mode), for the relevant timing
information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the SFC. See Figure 22, Synchronous PAF Flag - IDT Standard Mode and
FWFT Mode, for the relevant timing information.
the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the SFC. The offset “n” is the empty offset value.
The default setting for this value is in Table 10, Device Configuration.
the SFC. See Figure 21, Synchronous PAE Flag - IDT Standard Mode and
FWFT Mode, for the relevant timing information.
the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK.
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
In IDT Standard mode, EF is a double register-buffered output. In FWFT
The Programmable Almost-Full flag (PAF) will go LOW when the SFC
If asynchronous PAF configuration is selected, the PAF is asserted LOW on
The Programmable Almost-Empty flag (PAE) will go LOW when the SFC
In FWFT mode, the PAE will go LOW when there are n+1 words or less in
If asynchronous PAE configuration is selected, the PAE is asserted LOW on
EF/OR is synchronous and updated on the rising edge of RCLK.
26
DATA OUTPUTS (Q
for 24-bit wide data or (Q
MEMORY CLOCK OUTPUT (CK)
input.
MEMORY CLOCK OUTPUT INVERTED (CK)
clock input.
MEMORY BANK ADDRESS INPUT BIT (BA[1:0])
address input bits.
MEMORY COLUMN ADDRESS STROBE (CAS)
address strobe input.
MEMORY ADDRESS BUS (A[12:0])
bus.
MEMORY WRITE ENABLE (WE)
enable.
MEMORY ROW ADDRESS STROBE (RAS)
address strobe input.
BI-DIRECTIONAL I/O
MEMORY DATA INPUTS/OUTPUTS DQ[63:0]
bus.
MEMORY DATA STROBE OUTPUT DQS[7:0]
inputs.
(Q
These signals are to be connected to the external DDR SDRAM's clock
These signals are to be connected to the external DDR SDRAM's differential
These signals are to be connected to the external DDR SDRAM's bank
These signals are to be connected to the external DDR SDRAM's column
These signals are to be connected to the external DDR SDRAM's address
These signals are to be connected to the external DDR SDRAM's write
These signals are to be connected to the external DDR SDRAM's row
These signals are to be connected to the external DDR SDRAM's data input
These signals are to be connected to the external DDR SDRAM's data strobe
0
-Q
47
) are data outputs for 48-bit wide data, (Q
0
-Q
47
0
-Q
)
11
) are data outputs for 12-bit wide data.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
0
- Q
23
) are data outputs