IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 7

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PIN DESCRIPTIONS
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
BM
D[35:0]
Din
DF
DFM
ESTR
ESYNC
EXI
EXO
FF
FM
FSTR
Symbol
(1)
(1)
(1)
Bus Matching
Data Input Bus
Default Flag
Default Mode
PAEn Flag Bus
Strobe
PAEn Bus Sync
PAEn/PRn Bus
Expansion In
PAEn/PRn Bus
Expansion Out
Full Flag
Flag Mode
PAFn Flag Bus
Strobe
Name
I/O TYPE
OUTPUT during Polled operation of the PAEn bus. During Polled operation each devices queue status flags are
OUTPUT PAEn/PRn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’.
OUTPUT for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
INPUT
LVTTL
INPUT
This pin is setup before Master Reset and must not toggle during any device operation. This pin is used
along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3
for details.
These are the 36 data input pins. Data is written into the device via these input pins on the rising edge
of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet
markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs
may be used, any unused inputs should be tied LOW.
If the user requires default programming of the multi-queue device, this pin must be setup before Master
Reset and must not toggle during any device operation. The state of this input at master reset determines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
The multi-queue device requires programming after master reset. The user can do this serially via the
serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
and the RDADD bus to select a device for its queues to be placed on to the PAEn bus outputs. A device
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus
selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus
loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads device 1
on to PAEn, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle that a selected
device is placed on to the PAEn bus, the ESYNC output will be HIGH.
The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn/
PRn bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The
EXI receives a token from the previous device in a chain. In single device mode the EXI input must be
tied LOW if the PAEn/PRn bus is operated in direct mode. If the PAEn/PRn bus is operated in polled mode
the EXI input must be connected to the EXO output of the same device. In expansion mode the EXI of
the first device should be tied LOW, when direct mode is selected.
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
This pin pulses HIGH when device N places its PAE status on to the PAEn/PRn bus with respect to RCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAEn/PRn bus. This continues through the
chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each
device in the chain provides synchronization to the user of this looping event.
This pin provides the full flag output for the active queue, that is, the queue selected on the input port
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during
expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common
line. The device with a queue selected takes control of the FF bus, all other devices place their FF output
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
This pin is setup before a master reset and must not toggle during any device operation. The state of the
FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either
Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a device for its queues to be placed on to the PAFn bus outputs. A device
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
7
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES