IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 27

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PAFn BUS EXPANSION - DIRECT MODE
(addressed) mode. In direct mode the user can address the device they require
to control the PAFn bus. The address present on the 3 most significant bits of
the WRADD[4:0] address bus with FSTR (PAF flag strobe), HIGH will be
selected as the device on a rising edge of WCLK. So to address the first device
in a bank of devices the WRADD[4:0] address should be “000xx” the second
device “001xx” and so on. The 3 most significant bits of the WRADD[4:0] address
bus correspond to the device ID inputs ID[2:0]. The PAFn bus will change status
to show the new device selected 1 WCLK cycle after device selection. Note, that
if a read or write operation is occurring to a specific queue, say queue ‘x’ on
the same cycle as a PAFn bus switch to the device containing queue ‘x’, then
there may be an extra WCLK cycle delay before that queues status is correctly
shown on the respective output of the PAFn bus. However, the “active” PAF
flag will show correct status at all times.
controlling the PAFn bus can change every WCLK cycle. Also, data present
on the input bus, Din, can be written into a queue on the same WLCK rising edge
that a device is being selected on the PAFn bus, the only restriction being that
a write queue selection and PAFn bus selection cannot be made on the same cycle.
PAFn BUS EXPANSION– POLLED MODE
mode. In polled mode the PAFn bus automatically cycles through the devices
connected in expansion. In expansion mode one device will be set as the
Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The
master device is the first device to take control of the PAFn bus and place the
PAF status of its queues onto the bus on the first rising edge of WCLK after the
MRS input goes HIGH once a Master Reset is complete. The FSYNC (PAF sync
pulse) output of the first device (master device), will be HIGH for one cycle of
WCLK indicating that it is has control of the PAFn bus for that cycle.
device assuming control of the PAFn bus on the next WCLK cycle. This token
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn
Expansion Out” and “PAFn Expansion In”). The FXO output of the first device
connecting to the FXI input of the second device in the chain, the FXO of the
second device connects to the FXI of the third device and so on. The FXO of
the final device in a chain connects to the FXI of the first device, so that once the
PAFn bus has cycled through all devices control is again passed to the first
device. The FXO output of a device will be HIGH for the WCLK cycle it has control
of the bus.
PAEn/PRn FLAG BUS OPERATION
can be configured for up to 4 queues, each queue having its own almost empty/
packet ready status. An active queue has its flag status output to the discrete flags,
OV, PAE and PR, on the read port. Queues that are not selected for a read
operation can have their PAE/PR status monitored via the PAEn/PRn bus. The
PAEn/PRn flag bus is 4 bits wide, so that all 4 queues can have their status output
to the bus. The multi-queue device can provide either “Almost Empty” status or
“Packet Ready” status via the PAEn/PRn bus of its queues, depending on which
has been selected via the PKT (Packet) input during a master reset. If PKT is
HIGH then packet mode is selected and the PAEn/PRn bus will provide “Packet
Ready” status. If it is LOW then the PAEn/PRn bus will provide “Almost Empty”
status. In either case the operation of the bus is the same the difference being
that the bus is providing “Packet Ready” status versus “Almost Empty” status.
be set-up within the part, each queue having its own dedicated PAEn/PRn flag
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
If FM is LOW at Master Reset then the PAFn bus operates in Direct
Devices can be selected on consecutive WCLK cycles, that is the device
If FM is HIGH at Master Reset then the PAFn bus operates in Polled (Looped)
The device also passes a “token” onto the next device in the chain, the next
Please refer to Figure 28, PAF n Bus – Polled Mode for timing information.
The IDT72V51236/72V51246/72V51256 multi-queue flow-control devices
When a single multi-queue device is used anywhere from 1 to 4 queues may
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output on the PAEn/PRn bus. Queues 1 through 4 have their PAE/PR status
to PAE[0] through PAE[3] respectively. If less than 4 queues are used then only
the associated PAEn/PRn outputs will be required, unused PAEn/PRn outputs
will be don’t care outputs. When devices are connected in expansion mode the
PAEn/PRn flag bus can also be expanded beyond 4 bits to produce a wider
PAEn/PRn bus that encompasses all queues.
together to form a single 4 bit bus, i.e. PAE[0] of device 1 will connect to PAE[0]
of device 2 etc. When connecting devices in this manner the PAEn/PRn bus can
only be driven by a single device at any time, (the PAEn/PRn outputs of all other
devices must be in high impedance state). There are two methods by which the
user can select which device has control of the bus, these are “Direct”
(Addressed) mode or “Polled” (Looped) mode, determined by the state of the
FM (flag Mode) input during a Master Reset.
PAEn/PRn BUS EXPANSION- DIRECT MODE
(addressed) mode. In direct mode the user can address the device they require
to control the PAEn/PRn bus. The address present on the 3 most significant bits
of the RDADD[5:0] address bus with ESTR (PAE/PR flag strobe), HIGH will
be selected as the device on a rising edge of RCLK. So to address the first device
in a bank of devices the RDADD[5:0] address should be “000xx” the second
device “001xx” and so on. The 3 most significant bits of the RDADD[5:0] address
bus correspond to the device ID inputs ID[2:0]. The PAEn/PRn bus will change
status to show the new device selected 1 RCLK cycle after device selection.
Note, that if a read or write operation is occurring to a specific queue, say queue
‘x’ on the same cycle as a PAEn/PRn bus switch to the device containing queue
‘x’, then there may be an extra RCLK cycle delay before that queues status is
correctly shown on the respective output of the PAEn/PRn bus. However, the
“active” PAE and/or PR flag will show correct status at all times.
controlling the PAEn/PRn bus can change every RCLK cycle. Also, data can
be read out of a queue on the same RCLK rising edge that a device is being
selected on the PAEn/PRn bus, the only restriction being that a read queue
selection and PAEn/PRn bus selection cannot be made on the same cycle.
PAEn/PRn BUS EXPANSION- POLLED MODE
(Looped) mode. In polled mode the PAEn/PRn bus automatically cycles through
the devices connected in expansion. In expansion mode one device will be set
as the Master, MAST input tied HIGH, all other devices will have MAST tied LOW.
The master device is the first device to take control of the PAEn/PRn bus and
place the PAE/PR status of its queues onto the bus on the first rising edge of RCLK
after the MRS input goes HIGH once a Master Reset is complete. The ESYNC
(PAE/PR sync pulse) output of the first device (master device), will be HIGH for
one cycle of RCLK indicating that it is has control of the PAEn/PRn bus for that
cycle.
device assuming control of the PAEn/PRn bus on the next RCLK cycle. This
token passing is done via the EXO outputs and EXI inputs of the devices (“PAEn/
PRn Expansion Out” and “PAEn/PRn Expansion In”). The EXO output of the
first device connecting to the EXI input of the second device in the chain, the EXO
of the second device connects to the EXI of the third device and so on. The EXO
of the final device in a chain connects to the EXI of the first device, so that once
the PAEn/PRn bus has cycled through all devices control is again passed to
the first device. The EXO output of a device will be HIGH for the RCLK cycle
it has control of the bus.
information.
Alternatively, the 4 bit PAEn/PRn flag bus of each device can be connected
If FM is LOW at Master Reset then the PAEn/PRn bus operates in Direct
Devices can be selected on consecutive RCLK cycles, that is the device
If FM is HIGH at Master Reset then the PAEn/PRn bus operates in Polled
The device also passes a “token” onto the next device in the chain, the next
Please refer to Figure 29, PAE n/ PR n Bus – Polled Mode for timing
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES